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dc.contributor.authorGuirado, Robert
dc.contributor.authorKwon, Hyoukjun
dc.contributor.authorAlarcón Cot, Eduardo José
dc.contributor.authorAbadal Cavallé, Sergi
dc.contributor.authorKrishna, Tushar
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2021-03-02T09:58:29Z
dc.date.issued2019
dc.identifier.citationGuirado, R. [et al.]. Understanding the impact of on-chip communication on DNN accelerator performance. A: IEEE International Conference on Electronics, Circuits and Systems. "ICECS 2019: IEEE International Conference on Electronics, Circuits and Systems: Genoa, Italy: November 27-29, 2019: proceedings book". 2019, ISBN 978-1-7281-0996-1. DOI 10.1109/ICECS46596.2019.8964858.
dc.identifier.isbn978-1-7281-0996-1
dc.identifier.otherhttps://arxiv.org/pdf/1912.01664.pdf
dc.identifier.urihttp://hdl.handle.net/2117/340698
dc.description.abstractDeep Neural Networks have flourished at an unprecedented pace in recent years. They have achieved outstanding accuracy in fields such as computer vision, natural language processing, medicine or economics. Specifically, Convolutional Neural Networks (CNN) are particularly suited to object recognition or identification tasks. This, however, comes at a high computational cost, prompting the use of specialized GPU architectures or even ASICs to achieve high speeds and energy efficiency. ASIC accelerators streamline the execution of certain dataflows amenable to CNN computation that imply the constant movement of large amounts of data, thereby turning on-chip communication into a critical function within the accelerator. This paper studies the communication flows within CNN inference accelerators of edge devices, with the aim to justify current and future decisions in the design of the on-chip networks that interconnect their processing elements. Leveraging this analysis, we then qualitatively discuss the potential impact of introducing the novel paradigm of wireless on-chip network in this context.
dc.language.isoeng
dc.subjectÀrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal
dc.subject.lcshOperations research
dc.subject.otherAI chips
dc.subject.otherapplication specific integrated circuits
dc.subject.otherconvolutional neural nets
dc.subject.othergraphics processing units
dc.subject.otherobject recognition
dc.titleUnderstanding the impact of on-chip communication on DNN accelerator performance
dc.typeConference report
dc.subject.lemacInvestigació operativa
dc.contributor.groupUniversitat Politècnica de Catalunya. EPIC - Energy Processing and Integrated Circuits
dc.contributor.groupUniversitat Politècnica de Catalunya. CBA - Sistemes de Comunicacions i Arquitectures de Banda Ampla
dc.identifier.doi10.1109/ICECS46596.2019.8964858
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8964858
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac30582974
dc.description.versionPostprint (author's final draft)
dc.date.lift10000-01-01
local.citation.authorGuirado, R.; Kwon, H.; Alarcon, E.; Abadal, S.; Krishna, T.
local.citation.contributorIEEE International Conference on Electronics, Circuits and Systems
local.citation.publicationNameICECS 2019: IEEE International Conference on Electronics, Circuits and Systems: Genoa, Italy: November 27-29, 2019: proceedings book


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