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Understanding the impact of on-chip communication on DNN accelerator performance
dc.contributor.author | Guirado, Robert |
dc.contributor.author | Kwon, Hyoukjun |
dc.contributor.author | Alarcón Cot, Eduardo José |
dc.contributor.author | Abadal Cavallé, Sergi |
dc.contributor.author | Krishna, Tushar |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2021-03-02T09:58:29Z |
dc.date.issued | 2019 |
dc.identifier.citation | Guirado, R. [et al.]. Understanding the impact of on-chip communication on DNN accelerator performance. A: IEEE International Conference on Electronics, Circuits and Systems. "ICECS 2019: IEEE International Conference on Electronics, Circuits and Systems: Genoa, Italy: November 27-29, 2019: proceedings book". 2019, ISBN 978-1-7281-0996-1. DOI 10.1109/ICECS46596.2019.8964858. |
dc.identifier.isbn | 978-1-7281-0996-1 |
dc.identifier.other | https://arxiv.org/pdf/1912.01664.pdf |
dc.identifier.uri | http://hdl.handle.net/2117/340698 |
dc.description.abstract | Deep Neural Networks have flourished at an unprecedented pace in recent years. They have achieved outstanding accuracy in fields such as computer vision, natural language processing, medicine or economics. Specifically, Convolutional Neural Networks (CNN) are particularly suited to object recognition or identification tasks. This, however, comes at a high computational cost, prompting the use of specialized GPU architectures or even ASICs to achieve high speeds and energy efficiency. ASIC accelerators streamline the execution of certain dataflows amenable to CNN computation that imply the constant movement of large amounts of data, thereby turning on-chip communication into a critical function within the accelerator. This paper studies the communication flows within CNN inference accelerators of edge devices, with the aim to justify current and future decisions in the design of the on-chip networks that interconnect their processing elements. Leveraging this analysis, we then qualitatively discuss the potential impact of introducing the novel paradigm of wireless on-chip network in this context. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Enginyeria de la telecomunicació::Processament del senyal |
dc.subject.lcsh | Operations research |
dc.subject.other | AI chips |
dc.subject.other | application specific integrated circuits |
dc.subject.other | convolutional neural nets |
dc.subject.other | graphics processing units |
dc.subject.other | object recognition |
dc.title | Understanding the impact of on-chip communication on DNN accelerator performance |
dc.type | Conference report |
dc.subject.lemac | Investigació operativa |
dc.contributor.group | Universitat Politècnica de Catalunya. EPIC - Energy Processing and Integrated Circuits |
dc.contributor.group | Universitat Politècnica de Catalunya. CBA - Sistemes de Comunicacions i Arquitectures de Banda Ampla |
dc.identifier.doi | 10.1109/ICECS46596.2019.8964858 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | https://ieeexplore.ieee.org/document/8964858 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 30582974 |
dc.description.version | Postprint (author's final draft) |
dc.date.lift | 10000-01-01 |
local.citation.author | Guirado, R.; Kwon, H.; Alarcon, E.; Abadal, S.; Krishna, T. |
local.citation.contributor | IEEE International Conference on Electronics, Circuits and Systems |
local.citation.publicationName | ICECS 2019: IEEE International Conference on Electronics, Circuits and Systems: Genoa, Italy: November 27-29, 2019: proceedings book |