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Implicit transactional memory in chip multiprocessors
dc.contributor.author | Galluzzi, Marco |
dc.contributor.author | Vallejo, Enrique |
dc.contributor.author | Cristal Kestelman, Adrián |
dc.contributor.author | Vallejo, Fernando |
dc.contributor.author | Beivide Palacio, Ramon |
dc.contributor.author | Stenström, Per |
dc.contributor.author | Smith, James E. |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-09-28T10:35:08Z |
dc.date.available | 2017-09-28T10:35:08Z |
dc.date.issued | 2007-06 |
dc.identifier.citation | Galluzzi, M., Vallejo, E., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J., Valero, M. "Implicit transactional memory in chip multiprocessors". 2007. |
dc.identifier.uri | http://hdl.handle.net/2117/108083 |
dc.description.abstract | Chip Multiprocessors (CMPs) are an efficient way of designing and use the huge amount of transistors on a chip. Different cores on a chip can compose a shared memory system with a very low-latency interconnect at a very low cost. Unfortunately, consistency models and synchronization styles of popular programming models for multiprocessors impose severe performance losses. Known architectural approaches to combat these losses are too complex, too specialized, or not transparent to the software. In this article, we introduce “implicit transactional memory” as a generalized architectural concept to remove such performance losses. We show how the concept of implicit transactions can be implemented at a low complexity by leveraging the multi-checkpoint mechanism of the Kilo-Instruction Processor. By relying on a general speculation substrate, it supports even the strictest consistency model – sequential consistency – potentially as effectively as weaker models and it allows multiple threads to speculatively execute critical sections, beyond barriers and event synchronizations. |
dc.format.extent | 16 p. |
dc.language.iso | eng |
dc.relation.ispartofseries | UPC-DAC-RR-CAP-2007-14 |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Multiprocessors |
dc.subject.other | Kilo-instruction |
dc.subject.other | Multiprocessor |
dc.subject.other | Implicit transaction |
dc.subject.other | Memory consistency |
dc.title | Implicit transactional memory in chip multiprocessors |
dc.type | External research report |
dc.subject.lemac | Multiprocessadors |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.rights.access | Open Access |
local.identifier.drac | 514072 |
dc.description.version | Postprint (published version) |
local.citation.author | Galluzzi, M.; Vallejo, E.; Cristal, A.; Vallejo, F.; Beivide, R.; Stenström, P.; Smith, J.; Valero, M. |
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