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dc.contributor.authorGalluzzi, Marco
dc.contributor.authorVallejo, Enrique
dc.contributor.authorCristal Kestelman, Adrián
dc.contributor.authorVallejo, Fernando
dc.contributor.authorBeivide Palacio, Ramon
dc.contributor.authorStenström, Per
dc.contributor.authorSmith, James E.
dc.contributor.authorValero Cortés, Mateo
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-09-28T10:35:08Z
dc.date.available2017-09-28T10:35:08Z
dc.date.issued2007-06
dc.identifier.citationGalluzzi, M., Vallejo, E., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J., Valero, M. "Implicit transactional memory in chip multiprocessors". 2007.
dc.identifier.urihttp://hdl.handle.net/2117/108083
dc.description.abstractChip Multiprocessors (CMPs) are an efficient way of designing and use the huge amount of transistors on a chip. Different cores on a chip can compose a shared memory system with a very low-latency interconnect at a very low cost. Unfortunately, consistency models and synchronization styles of popular programming models for multiprocessors impose severe performance losses. Known architectural approaches to combat these losses are too complex, too specialized, or not transparent to the software. In this article, we introduce “implicit transactional memory” as a generalized architectural concept to remove such performance losses. We show how the concept of implicit transactions can be implemented at a low complexity by leveraging the multi-checkpoint mechanism of the Kilo-Instruction Processor. By relying on a general speculation substrate, it supports even the strictest consistency model – sequential consistency – potentially as effectively as weaker models and it allows multiple threads to speculatively execute critical sections, beyond barriers and event synchronizations.
dc.format.extent16 p.
dc.language.isoeng
dc.relation.ispartofseriesUPC-DAC-RR-CAP-2007-14
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshMultiprocessors
dc.subject.otherKilo-instruction
dc.subject.otherMultiprocessor
dc.subject.otherImplicit transaction
dc.subject.otherMemory consistency
dc.titleImplicit transactional memory in chip multiprocessors
dc.typeExternal research report
dc.subject.lemacMultiprocessadors
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.rights.accessOpen Access
local.identifier.drac514072
dc.description.versionPostprint (published version)
local.citation.authorGalluzzi, M.; Vallejo, E.; Cristal, A.; Vallejo, F.; Beivide, R.; Stenström, P.; Smith, J.; Valero, M.


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