Ara es mostren els items 1-20 de 45

    • Accurate ILP-Based Contention Modeling on Statically Scheduled Multicore Systems 

      Palomo, Xavier; Mezzetti, Enrico; Abella Ferrer, Jaume; Bril, Reinder J.; Cazorla, Francisco J. (IEEE, 2019-06-24)
      Comunicació de congrés
      Accés obert
      Commercially available Off The Shelf (COTS) multicores have been assessed as the baseline computing platform even in the most conservative real-time domains. Multicore contention arising on shared hardware resources, with ...
    • Accurately measuring contention in Mesh NoCs in time-sensitive embedded systems 

      Cardona Nadal, Jordi; Hernández Luz, Carles; Abella Ferrer, Jaume; Mezzetti, Enrico; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2023-05)
      Article
      Accés obert
      The computing capacity demanded by embedded systems is on the rise as software implements more functionalities, ranging from best-effort entertainment functions to performance-guaranteed safety-related functions. Heterogeneous ...
    • ASCOM: Affordable Sequence-aware COntention Modeling in crossbar-based MPSoCs 

      Giesen León, Jeremy Jens; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2023)
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      Multicore interference that arises when several accesses contend for the same shared hardware resources poses a challenge to the already demanding consolidated verification and validation practice. The Sequence-Aware Pairing ...
    • AURIX TC277 Multicore Contention Model Integration for Automotive Applications 

      Mezzetti, Enrico; Barbina, Luca; Abella Ferrer, Jaume; Botta, Stefania; Cazorla, Francisco J. (IEEE, 2019-05-16)
      Comunicació de congrés
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      The ability to produce early guaranteed performance (worst-case execution time) estimates for multicores, i.e. before software from different providers gets integrated onto the same critical system, is pivotal. This helps ...
    • ePAPI: Performance Application ProgrammingInterface for Embedded Platforms 

      Giesen, Jeremy; Mezzetti, Enrico; Abella Ferrer, Jaume; Fernández, Enrique; Cazorla, Francisco J. (2019)
      Comunicació de congrés
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      Performance Monitoring Counters (PMCs) have been traditionally used in the mainstream computing domain to perform debugging and optimization of software performance. PMCs are increasingly considered in embedded time-critical ...
    • EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application 

      Mezzetti, Enrico; Fernandez, Mikel; Bardizbanyan, Alen; Agirre, Irune; Abella Ferrer, Jaume; Vardanega, Tullio; Cazorla, Francisco J. (Institute of Electrical and Electronics Engineers (IEEE), 2017-06-08)
      Comunicació de congrés
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      Measurement-based timing analysis approaches are increasingly making their way into several industrial domains on account of their good cost-benefit ratio. The trustworthiness of those methods, however, suffers from the ...
    • EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis 

      Ziccardi, Marco; Mezzetti, Enrico; Vardanega, Tullio; Abella Ferrer, Jaume; Cazorla, Francisco J. (IEEE, 2016-01-18)
      Comunicació de congrés
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      Measurement-based probabilistic timing analysis (MBPTA) computes trustworthy upper bounds to the execution time of software programs. MBPTA has the connotation, typical of measurement-based techniques, that the bounds ...
    • Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262 

      Agirre, Irune; Cazorla, Francisco J.; Abella Ferrer, Jaume; Hernandez, Carles; Mezzetti, Enrico; Azkarate-askasua, Mikel; Vardanega, Tullio (IEEE, 2018-09-01)
      Accés obert
      Car manufacturers relentlessly replace or augment the functionality of mechanical subsystems with electronic components. Most such subsystems (e.g., steer-by-wire) are safety related, hence, subject to regulation. ISO-26262, ...
    • Generating and Exploiting Deep Learning Variants to Increase Heterogeneous Resource Utilization in the NVIDIA Xavier 

      Pujol, Roger; Tabani, Hamid; Kosmidis, Leonidas; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla, Francisco J. (2019)
      Comunicació de congrés
      Accés obert
      Deep learning-based solutions and, in particular, deep neural networks (DNNs) are at the heart of several functionalities in critical-real time embedded systems (CRTES) from vision-based perception (object detection and ...
    • High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V 

      Mezzetti, Enrico; Kosmidis, Leonidas; Abella Ferrer, Jaume; Cazorla, Francisco J. (IEEE, 2018-01-16)
      Article
      Accés obert
      As software continues to control more system-critical functions in cars, its timing is becoming an integral element in functional safety. Timing validation and verification (V&V) assesses softwares end-to-end timing ...
    • HRM: merging hardware event monitors for improved timing analysis of complex MPSoCs 

      Vilardell Moreno, Sergi; Serra Mochales, Isabel; Santalla, Roberto; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (2020-11)
      Article
      Accés obert
      The Performance Monitoring Unit (PMU) in MPSoCs is at the heart of the latest measurement-based timing analysis techniques in Critical Embedded Systems. In particular, hardware event monitors (HEMs) in the PMU are used as ...
    • Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems 

      Fernández de Lecea, Asier; Hassan, Mohamed; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Comunicació de congrés
      Accés obert
      Main memory is one of the most complex resources to analyze in multicore-based embedded real-time systems, with contention in the memory controller and the timing constraints of the main memory device as the main contributors ...
    • Increasing the Reliability of Software Timing Analysis for Cache-Based Processors 

      Milutinovic, Suzana; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla, Francisco J. (IEEE, 2019-06-01)
      Article
      Accés obert
      Real-time systems are witnessing a significant increase in critical software's size, complexity, and performance needs, which can only be satisfied with high-performance hardware features. Cache memories, pervasively used ...
    • Leveraging hardware QoS to control contention in the Xilinx Zynq UltraScale+ MPSoC 

      Serrano Cases, Alejandro; Reina, Juan M.; Abella Ferrer, Jaume; Mezzetti, Enrico; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2021)
      Text en actes de congrés
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      The interference co-running tasks generate on each other’s timing behavior continues to be one of the main challenges to be addressed before Multi-Processor System-on-Chip (MPSoCs) are fully embraced in critical systems ...
    • Main sources of variability and non-determinism in AD software: taxonomy and prospects to handle them 

      Alcón Doganoc, Miguel; Brando Guillaumes, Axel; Mezzetti, Enrico; Abella Ferrer, Jaume; Cazorla Almeida, Francisco Javier (Springer Nature, 2023-09)
      Article
      Accés restringit per política de l'editorial
      Safety standards in domains like automotive and avionics seek for deterministic execution (lack of jittery behavior) as a stepping stone to build a certification argument on the correct timing behavior of the system. ...
    • MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding 

      Díaz, Enrique; Fernández, Mikel; Kosmidis, Leonidas; Mezzetti, Enrico; Hernandez, Carles; Abella Ferrer, Jaume; Cazorla, Francisco J. (Springer International Publishing, 2017-05-30)
      Comunicació de congrés
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      In critical domains, reliable software execution is increasingly involving aspects related to the timing dimension. This is due to the advent of high-performance (complex) hardware, used to provide the rising levels of ...
    • Measurement-based cache representativeness on multipath programs 

      Milutinovic, Suzana; Abella Ferrer, Jaume; Mezzetti, Enrico; Cazorla Almeida, Francisco Javier (Association for Computing Machinery (ACM), 2018-06)
      Comunicació de congrés
      Accés obert
      Autonomous vehicles in embedded real-time systems increase critical-software size and complexity whose performance needs are covered with high-performance hardware features like caches, which however hampers obtaining WCET ...
    • Measurement-based probabilistic timing analysis for multi-path programs 

      Cucu Grosjean, Liliana; Santinelli, Luca; Houston, Michael; Lo, Code; Vardanega, Tulio; Kosmidis, Leonidas; Abella Ferrer, Jaume; Mezzetti, Enrico; Quiñones, Eduardo; Cazorla Almeida, Francisco Javier (2012)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      The rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ...
    • Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study 

      Wartel, Franck; Kosmidis, Leonidas; Lo, Code; Triquet, Benoit; Quiñones, Eduardo; Abella Ferrer, Jaume; Gogonel, Adriana; Baldovin, Andrea; Mezzetti, Enrico; Cucu Grosjean, Liliana; Vardanega, Tulio; Cazorla Almeida, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Probabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ...
    • Measurement-based timing analysis of the AURIX caches 

      Kosmidis, Leonidas; Compagnin, Davide; Morales, David; Mezzetti, Enrico; Quiñones, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
      Text en actes de congrés
      Accés obert
      Cache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has ...