Browsing by Author "Armejach Sanosa, Adrià"
Now showing items 1-20 of 20
-
A FM-index transformation to enable large k-steps
(Barcelona Supercomputing Center, 2019-05-07)
Conference report
Open Access -
Compressed sparse FM-index: Fast sequence alignment using large K-steps
(2022-01-01)
Article
Open AccessThe FM-index is a data structure used in genomics for exact search of input sequences over large reference genomes. Algorithms based on the FM-index show an irregular memory access pattern, resulting in a memory bound ... -
Design space exploration of next-generation HPC machines
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Conference report
Restricted access - confidentiality agreementThe landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. With the goal of improving the efficiency of next-generation large HPC systems, designers ... -
Design trade-offs for emerging HPC processors based on mobile market technology
(2019-09-01)
Article
Open AccessHigh-performance computing (HPC) is at the crossroads of a potential transition toward mobile market processor technology. Unlike in prior transitions, numerous hardware vendors and integrators will have access to ... -
Dynamically adapting floating-point precision to accelerate deep neural network training
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessMixed-precision (MP) arithmetic combining both single- and half-precision operands has been successfully applied to train deep neural networks. Despite its advantages in terms of reducing the need for key resources like ... -
Evaluating mixed-precision arithmetic for 3D generative adversarial networks to simulate high energy physics detectors
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Conference report
Open AccessSeveral hardware companies are proposing native Brain Float 16-bit (BF16) support for neural network training. The usage of Mixed Precision (MP) arithmetic with floating-point 32-bit (FP32) and 16-bit half-precision aims ... -
Exploration of architectural parameters for future HPC systems
(Barcelona Supercomputing Center, 2019-05-07)
Conference report
Open Access -
gem5 + rtl: A framework to enable RTL models inside a full-system simulator
(Association for Computing Machinery (ACM), 2021)
Conference report
Open AccessIn recent years there has been a surge of interest in designing custom accelerators for power-efficient high-performance computing. However, available tools to simulate low-level RTL designs often neglect the target system ... -
Hardware acceleration for query processing: Leveraging FPGAs, CPUs, and memory
(2016-01)
Article
Open AccessDatabase management systems have become an indispensable tool for industry, government, and academia, and form a significant component of modern datacenters. They can be used in a multitude of scenarios, including online ... -
HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Conference report
Open AccessHardware Transactional Memory (HTM) exposes parallelism by allowing possibly conflicting sections of code, called transactions, to execute concurrently in multithreaded applications. However, conflicts among concurrent ... -
Implications of non-volatile memory as primary storage for database management systems
(IEEE, 2017-01-19)
Conference report
Open AccessTraditional Database Management System (DBMS) software relies on hard disks for storing relational data. Hard disks are cheap, persistent, and offer huge storage capacities. However, data retrieval latency for hard disks ... -
Mont-Blanc 2020: Towards scalable and power efficient European HPC processors
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessThe Mont-Blanc 2020 (MB2020) project has triggered the development of the next generation industrial processor for Big Data and High Performance Computing (HPC). MB2020 is paving the way to the future low-power European ... -
Multilevel simulation-based co-design of next generation HPC microprocessors
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Conference report
Open AccessThis paper demonstrates the combined use of three simulation tools in support of a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation tools make different trade-offs between simulation ... -
On the use of many-core Marvell ThunderX2 processor for HPC workloads
(2021)
Article
Open AccessMarvell’s ThunderX2 has been the first Arm-based processor with deployments in large-scale HPC production systems, challenging the dominance that x86 processors had in the last decades. While x86 processors and its software ... -
Parallel-Architecture Simulator Development Using Hardware Transactional Memory
(Universitat Politècnica de Catalunya, 2009-09-23)
Master thesis
Open AccessTo address the need for a simpler parallel programming model, Transactional Memory (TM) has been developed and promises good parallel performance with easy-to-write parallel code. Unlike lock-based approaches, with TM, ... -
PLANAR: a programmable accelerator for near-memory data rearrangement
(Association for Computing Machinery (ACM), 2021)
Conference report
Open AccessMany applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques ... -
Stencil codes on a vector length agnostic architecture
(Association for Computing Machinery (ACM), 2018)
Conference report
Open AccessData-level parallelism is frequently ignored or underutilized. Achieved through vector/SIMD capabilities, it can provide substantial performance improvements on top of widely used techniques such as thread-level parallelism. ... -
Techniques to improve concurrency in hardware transactional memory
(Universitat Politècnica de Catalunya, 2014-06-13)
Doctoral thesis
Open AccessTransactional Memory (TM) aims to make shared memory parallel programming easier by abstracting away the complexity of managing shared data. The programmer defines sections of code, called transactions, which the TM system ... -
Towards resilient EU HPC systems: A blueprint
(2020-04)
Research report
Open AccessThis document aims to spearhead a Europe-wide discussion on HPC system resilience and to help the European HPC community define best practices for resilience. We analyse a wide range of state-of-the-art resilience mechanisms ... -
Using Arm’s scalable vector extension on stencil codes
(2020-03)
Article
Open AccessData-level parallelism is frequently ignored or underutilized. Achieved through vector/SIMD capabilities, it can provide substantial performance improvements on top of widely used techniques such as thread-level parallelism. ...
