Now showing items 1-20 of 20

    • A FM-index transformation to enable large k-steps 

      Langarita, Rubén; Armejach Sanosa, Adrià; Moreto Planas, Miquel (Barcelona Supercomputing Center, 2019-05-07)
      Conference report
      Open Access
    • Compressed sparse FM-index: Fast sequence alignment using large K-steps 

      Langarita Benítez, Rubén; Armejach Sanosa, Adrià; Setoain, Javier; Ibáñez Marín, Pablo Enrique; Alastruey Benedé, Jesús; Moreto Planas, Miquel (2022-01-01)
      Article
      Open Access
      The FM-index is a data structure used in genomics for exact search of input sequences over large reference genomes. Algorithms based on the FM-index show an irregular memory access pattern, resulting in a memory bound ...
    • Design space exploration of next-generation HPC machines 

      Gómez Crespo, Constantino; Martínez Palau, Francesc; Armejach Sanosa, Adrià; Moreto Planas, Miquel; Mantovani, Filippo; Casas Guix, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2019)
      Conference report
      Restricted access - confidentiality agreement
      The landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. With the goal of improving the efficiency of next-generation large HPC systems, designers ...
    • Design trade-offs for emerging HPC processors based on mobile market technology 

      Armejach Sanosa, Adrià; Casas, Marc; Moreto Planas, Miquel (2019-09-01)
      Article
      Open Access
      High-performance computing (HPC) is at the crossroads of a potential transition toward mobile market processor technology. Unlike in prior transitions, numerous hardware vendors and integrators will have access to ...
    • Dynamically adapting floating-point precision to accelerate deep neural network training 

      Osorio Ríos, John Haiber; Armejach Sanosa, Adrià; Petit, Eric; Henry, Greg; Casas Guix, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      Mixed-precision (MP) arithmetic combining both single- and half-precision operands has been successfully applied to train deep neural networks. Despite its advantages in terms of reducing the need for key resources like ...
    • Evaluating mixed-precision arithmetic for 3D generative adversarial networks to simulate high energy physics detectors 

      Osorio Ríos, John Haiber; Armejach Sanosa, Adrià; Khattak, Gulrukh; Petit, Eric; Vallecorsa, Sofia; Casas Guix, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2020)
      Conference report
      Open Access
      Several hardware companies are proposing native Brain Float 16-bit (BF16) support for neural network training. The usage of Mixed Precision (MP) arithmetic with floating-point 32-bit (FP32) and 16-bit half-precision aims ...
    • Exploration of architectural parameters for future HPC systems 

      Gómez, Constantino; Martínez, Francesc; Armejach Sanosa, Adrià; Casas, Marc; Mantovani, Filippo; Moreto Planas, Miquel (Barcelona Supercomputing Center, 2019-05-07)
      Conference report
      Open Access
    • gem5 + rtl: A framework to enable RTL models inside a full-system simulator 

      López Paradís, Guillem; Armejach Sanosa, Adrià; Moreto Planas, Miquel (Association for Computing Machinery (ACM), 2021)
      Conference report
      Open Access
      In recent years there has been a surge of interest in designing custom accelerators for power-efficient high-performance computing. However, available tools to simulate low-level RTL designs often neglect the target system ...
    • Hardware acceleration for query processing: Leveraging FPGAs, CPUs, and memory 

      Arcas Abella, Oriol; Armejach Sanosa, Adrià; Hayes, Timothy; Malazgirt, Görker Alp; Palomar Pérez, Óscar; Salami, Behzad; Sonmez, Nehir (2016-01)
      Article
      Open Access
      Database management systems have become an indispensable tool for industry, government, and academia, and form a significant component of modern datacenters. They can be used in a multitude of scenarios, including online ...
    • HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory 

      Armejach Sanosa, Adrià; Negi, Anurag; Cristal Kestelman, Adrián; Unsal, Osman Sabri; Stenström, Per; Harris, Tim (Institute of Electrical and Electronics Engineers (IEEE), 2013)
      Conference report
      Open Access
      Hardware Transactional Memory (HTM) exposes parallelism by allowing possibly conflicting sections of code, called transactions, to execute concurrently in multithreaded applications. However, conflicts among concurrent ...
    • Implications of non-volatile memory as primary storage for database management systems 

      Ul Mustafa, Naveed; Armejach Sanosa, Adrià; Ozturk, Ozcan; Cristal Kestelman, Adrián; Unsal, Osman Sabri (IEEE, 2017-01-19)
      Conference report
      Open Access
      Traditional Database Management System (DBMS) software relies on hard disks for storing relational data. Hard disks are cheap, persistent, and offer huge storage capacities. However, data retrieval latency for hard disks ...
    • Mont-Blanc 2020: Towards scalable and power efficient European HPC processors 

      Armejach Sanosa, Adrià; Brank, Bine; Cortina Guardia, Jordi; Dolique, François; Hayes, Timothy; Ho, Nam; Lagadec, Pierre-Axel; Lemaire, Romain; López Paradís, Guillem; Marliac, Laurent; Moreto Planas, Miquel; Marcuello Pascual, Pedro; Pleiter, Dirk; Tan, Xubin; Derradji, Said (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      The Mont-Blanc 2020 (MB2020) project has triggered the development of the next generation industrial processor for Big Data and High Performance Computing (HPC). MB2020 is paving the way to the future low-power European ...
    • Multilevel simulation-based co-design of next generation HPC microprocessors 

      Zaourar, Lilia; Benazouz, Mohamed; Mouhagir, Ayoub; Jebali, Fatma; Sassolas, Tanguy; Weill, Jean Christophe; Radulović, Milan; Martínez Palau, Francesc; Armejach Sanosa, Adrià; Casas Guix, Marc (Institute of Electrical and Electronics Engineers (IEEE), 2021)
      Conference report
      Open Access
      This paper demonstrates the combined use of three simulation tools in support of a co-design methodology for an HPC-focused System-on-a-Chip (SoC) design. The simulation tools make different trade-offs between simulation ...
    • On the use of many-core Marvell ThunderX2 processor for HPC workloads 

      Soria Pardos, Víctor; Armejach Sanosa, Adrià; Suárez Gracía, Dario; Moreto Planas, Miquel (2021)
      Article
      Open Access
      Marvell’s ThunderX2 has been the first Arm-based processor with deployments in large-scale HPC production systems, challenging the dominance that x86 processors had in the last decades. While x86 processors and its software ...
    • Parallel-Architecture Simulator Development Using Hardware Transactional Memory 

      Armejach Sanosa, Adrià (Universitat Politècnica de Catalunya, 2009-09-23)
      Master thesis
      Open Access
      To address the need for a simpler parallel programming model, Transactional Memory (TM) has been developed and promises good parallel performance with easy-to-write parallel code. Unlike lock-based approaches, with TM, ...
    • PLANAR: a programmable accelerator for near-memory data rearrangement 

      Barredo Ferreira, Adrián; Armejach Sanosa, Adrià; Beard, Jonathan C.; Moreto Planas, Miquel (Association for Computing Machinery (ACM), 2021)
      Conference report
      Open Access
      Many applications employ irregular and sparse memory accesses that cannot take advantage of existing cache hierarchies in high performance processors. To solve this problem, Data Layout Transformation (DLT) techniques ...
    • Stencil codes on a vector length agnostic architecture 

      Armejach Sanosa, Adrià; Caminal Pallarés, Helena; Cebrián González, Juan Manuel; González-Alberquilla, Rekai; Adeniyi-Jones, Chris; Valero Cortés, Mateo; Casas, Marc; Moreto Planas, Miquel (Association for Computing Machinery (ACM), 2018)
      Conference report
      Open Access
      Data-level parallelism is frequently ignored or underutilized. Achieved through vector/SIMD capabilities, it can provide substantial performance improvements on top of widely used techniques such as thread-level parallelism. ...
    • Techniques to improve concurrency in hardware transactional memory 

      Armejach Sanosa, Adrià (Universitat Politècnica de Catalunya, 2014-06-13)
      Doctoral thesis
      Open Access
      Transactional Memory (TM) aims to make shared memory parallel programming easier by abstracting away the complexity of managing shared data. The programmer defines sections of code, called transactions, which the TM system ...
    • Towards resilient EU HPC systems: A blueprint 

      Radojković, Petar; Marazakis, Manolis; Carpenter, Paul Matthew; Jeyapaul, Reiley; Gizopoulos, Dimitris; Schulz, Martin; Armejach Sanosa, Adrià; Ayguadé Parra, Eduard; Canal Corretger, Ramon; Moreto Planas, Miquel; Salami, Behzad; Unsal, Osman Sabri (2020-04)
      Research report
      Open Access
      This document aims to spearhead a Europe-wide discussion on HPC system resilience and to help the European HPC community define best practices for resilience. We analyse a wide range of state-of-the-art resilience mechanisms ...
    • Using Arm’s scalable vector extension on stencil codes 

      Armejach Sanosa, Adrià; Caminal Pallarés, Helena; Cebrián González, Juan Manuel; Langarita, Rubén; González-Alberquilla, Rekai; Adeniyi-Jones, Chris; Valero Cortés, Mateo; Casas Guix, Marc; Moreto Planas, Miquel (2020-03)
      Article
      Open Access
      Data-level parallelism is frequently ignored or underutilized. Achieved through vector/SIMD capabilities, it can provide substantial performance improvements on top of widely used techniques such as thread-level parallelism. ...