Design space exploration of next-generation HPC machines
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hdl:2117/329905
Document typeConference report
Defense date2019
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - confidentiality agreement
European Commission's projectMont-Blanc 3 - Mont-Blanc 3, European scalable and power efficient HPC platform based on low-power embedded technology (EC-H2020-671697)
Mont-Blanc 2020 - Mont-Blanc 2020, European scalable, modular and power efficient HPC processor (EC-H2020-779877)
Mont-Blanc 2020 - Mont-Blanc 2020, European scalable, modular and power efficient HPC processor (EC-H2020-779877)
Abstract
The landscape of High Performance Computing (HPC) system architectures keeps expanding with new technologies and increased complexity. With the goal of improving the efficiency of next-generation large HPC systems, designers require tools for analyzing and predicting the impact of new architectural features on the performance of complex scientific applications at scale. We simulate five hybrid (MPI+OpenMP) applications over 864 architectural proposals based on stateof-the-art and emerging HPC technologies, relevant both in industry and research. This paper significantly extends our previous work with MUltiscale Simulation Approach (MUSA) enabling accurate performance and power estimations of large-scale HPC systems. We reveal that several applications present critical scalability issues mostly due to the software parallelization approach. Looking at speedup and energy consumption exploring the design space (i.e., changing memory bandwidth, number of cores, and type of cores), we provide evidence-based architectural recommendations that will serve as hardware and software codesign guidelines.
CitationGomez, C. [et al.]. Design space exploration of next-generation HPC machines. A: IEEE International Parallel and Distributed Processing Symposium. "2019 IEEE International Parallel and Distributed Processing Symposium (IPDPS 2019): Rio de Janeiro, Brazili: 20-24 May 2019". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 54-65. ISBN 978-1-7281-1247-3. DOI 10.1109/IPDPS.2019.00017.
ISBN978-1-7281-1247-3
Publisher versionhttps://ieeexplore.ieee.org/document/8820990
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