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Reliability estimation at block-level granularity of spin-transfer-torque MRAMs
dc.contributor.author | Di Carlo, Stefano |
dc.contributor.author | Indaco, Marco |
dc.contributor.author | Prinetto, Paolo |
dc.contributor.author | Vatajelu, Elena Ioana |
dc.contributor.author | Rodríguez Montañés, Rosa |
dc.contributor.author | Figueras Pàmies, Joan |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica |
dc.date.accessioned | 2015-03-26T09:25:11Z |
dc.date.created | 2014 |
dc.date.issued | 2014 |
dc.identifier.citation | Stefano Di Carlo [et al.]. Reliability estimation at block-level granularity of spin-transfer-torque MRAMs. A: DFT - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. "DFT2014 - 27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems". Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 75-80. |
dc.identifier.isbn | 978-1-4799-6155-9 |
dc.identifier.uri | http://hdl.handle.net/2117/27040 |
dc.description.abstract | In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability and aging phenomena, making reliability prediction a growing concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve the desired reliability target for the memory under study. |
dc.format.extent | 6 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Sistemes d'informació |
dc.subject.lcsh | Computer storage devices -- Reliability |
dc.subject.other | Emerging memories |
dc.subject.other | STT-MRAM |
dc.subject.other | Memory reliability |
dc.title | Reliability estimation at block-level granularity of spin-transfer-torque MRAMs |
dc.type | Conference report |
dc.subject.lemac | Ordinadors -- Dispositius de memòria -- Fiabilitat |
dc.contributor.group | Universitat Politècnica de Catalunya. QINE - Disseny de Baix Consum, Test, Verificació i Circuits Integrats de Seguretat |
dc.identifier.doi | 10.1109/DFT.2014.6962093 |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 15543512 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Stefano Di Carlo; Indaco, M.; Paolo Prinetto; Vatajelu, E.; Rodriguez, R.; Figueras, J. |
local.citation.contributor | DFT - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems |
local.citation.publicationName | DFT2014 - 27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems |
local.citation.startingPage | 75 |
local.citation.endingPage | 80 |