PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
In recent years, the Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Under today aggressive technology scaling requirements, the STT-MRAM is affected by process variability and aging phenomena, making reliability prediction a growing concern. In this paper, we provide a methodology for predicting the reliability of an STT-MRAM based memory at block level for different block sizes and access rates. The proposed methodology also allows for an exploration of required error correction capabilities as function of code word size to achieve the desired reliability target for the memory under study.
CitationStefano Di Carlo [et al.]. Reliability estimation at block-level granularity of spin-transfer-torque MRAMs. A: DFT - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems. "DFT2014 - 27th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems". Institute of Electrical and Electronics Engineers (IEEE), 2014, p. 75-80.
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