Hybrid transactional memory to accelerate safe lock-based transactions

Abstract

To reduce the overhead of Software Transactional Memory (STM) there are many recent proposals to build hybrid systems that use architectural support either to accelerate parts of a particular STM algorithm (Ha-TM), or to form a hybrid system allowing hardware-transactions and software-transactions to inter-operate in the same address space (Hy-TM). In this paper we introduce a Hy-TM design based on multi-reader, single-writer locking when a transaction tries to commit. This approach is the first Hy-TM to combine three desirable features: (i) execution whether or not the architectural support is present, (ii) execution of a single common code path, whether a transaction is running in software or hardware, (iii) immunity, for correctly synchronized programs, from the “privatization” problem. Our architectural support can be any traditional HTM supporting bounded or unbounded-size transactions, along with an instruction to test whether or not the current thread is running inside a hardware transaction. With this we carefully design the Hy-TM so that portions of its work can be elided when running a transaction in hardware mode. While not compared with the native HTM system, our simulations show that, when running with HW support, the main runtime overheads of the STM system are elided: Depending on the workload, the speedup with read-only transactions is up to 3.03× in the single-thread execution and 61× in the 32-thread case, while with read-and-write transactions it reaches over 10×.