Power-efficient spilling techniques for chip multiprocessors
Tipus de documentText en actes de congrés
Condicions d'accésAccés restringit per política de l'editorial
Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the latency and high-demand of the on-chip network and the off-chip memory communication. To optimize the usage of on-chip memory space and reduce off-chip traffic several techniques have proposed to use the N-chance forwarding mechanism, a solution for distributing unused cache space in chip multiprocessors. This technique, however, can lead in some cases to extra unnecessary network traffic or inefficient cache allocation. This paper presents two alternative power-efficient spilling methods to improve the efficiency of the N-chance forwarding mechanism. Compared to traditional Spilling, our Distance-Aware Spilling technique provides an energy efficiency improvement (MIPS3/W) of 16% on average, and a reduction of the network usage of 14% in a ring configuration while increasing performance 6%. Our Selective Spilling technique is able to avoid most of the unnecessary reallocations and it doubles the reuse of spilled blocks, reducing network traffic by an average of 22%. A combination of both techniques allows to reduce the network usage by 30% on average without degrading performance, allowing a 9% increase of the energy efficiency.
CitacióHerrero, E.; González, J.; Canal, R. Power-efficient spilling techniques for chip multiprocessors. A: International Conference on Parallel and Distributed Computing. "16th. International Conference on Parallel and Distributed Computing". Ischia: Springer Verlag, 2010, p. 256-267.
Versió de l'editorhttp://www.springerlink.com/content/h355h2r488u3/#section=761352
|Power-efficient ... or chip mulitpocessors.pdf||333.6Kb||Accés restringit|