Enviaments recents

  • Exploiting path parallelism in logic programming 

    Tubella Murgadas, Jordi; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1995)
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    This paper presents a novel parallel implementation of Prolog. The system is based on Multipath, a novel execution model for Prolog that implements a partial breadth-first search of the SLD-tree. The paper focusses on the ...
  • A methodology for user-oriented scalability analysis 

    Royo Vallés, María Dolores; Valero García, Miguel; González Colás, Antonio María; Marí, Carme (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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    Scalability analysis provides information about the effectiveness of increasing the number of resources of a parallel system. Several methods have been proposed which use different approaches to provide this information. ...
  • A Jacobi-based algorithm for computing symmetric eigenvalues and eigenvectors in a two-dimensional mesh 

    Royo Vallés, María Dolores; Valero García, Miguel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1998)
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    The paper proposes an algorithm for computing symmetric eigenvalues and eigenvectors that uses a one-sided Jacobi approach and is targeted to a multicomputer in which nodes can be arranged as a two-dimensional mesh with ...
  • An efficient solver for Cache Miss Equations 

    Bermudo, Nerina; Vera Rivera, Francisco Javier; González Colás, Antonio María; Llosa Espuny, José Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2000)
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    Cache Miss Equations (CME) (S. Ghosh et al., 1997) is a method that accurately describes the cache behavior by means of polyhedra. Even though the computation cost of generating CME is a linear function of the number of ...
  • A quantitative assessment of thread-level speculation techniques 

    Marcuello Pascual, Pedro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2000)
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    Speculative thread-level parallelism has been recently proposed as an alternative source of parallelism that can boost the performance for applications where independent threads are hard to find. Several schemes to exploit ...
  • Near-optimal loop tiling by means of cache miss equations and genetic algorithms 

    Abella Ferrer, Jaume; González Colás, Antonio María; Llosa Espuny, José Francisco; Vera Rivera, Francisco Javier (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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    The effectiveness of the memory hierarchy is critical for the performance of current processors. The performance of the memory hierarchy can be improved by means of program transformations such as loop tiling, which is a ...
  • High-Performance low-vcc in-order core 

    Abella Ferrer, Jaume; Chaparro, Pedro; Vera Rivera, Francisco Javier; Carretero Casado, Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2010)
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    Power density grows in new technology nodes, thus requiring Vcc to scale especially in mobile platforms where energy is critical. This paper presents a novel approach to decrease Vcc while keeping operating frequency high. ...
  • Exploiting pseudo-schedules to guide data dependence graph partitioning 

    Aleta Ortega, Alexandre; Codina Viñas, Josep M.; Sánchez Navarro, F. Jesús; González Colás, Antonio María; David, Kaeli (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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    This paper presents a new modulo scheduling algorithm for clustered microarchitectures. The main feature of the proposed scheme is that the assignment of instructions to clusters is done by means of graph partitioning ...
  • Dynamic cluster resizing 

    González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2003)
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    Processor resources required for an effective execution of an application vary across different sections. We propose to take advantage of clustering to turn-off resources that do not contribute to improve performance. ...
  • Distributing the frontend for temperature reduction 

    Chaparro, Pedro; Magklis, Grigorios; González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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    Due to increasing power densities, both on-chip average and peak temperatures are fast becoming a serious bottleneck in processor design. This is due to the cost of removing the heat generated, and the performance impact ...

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