Enviaments recents

  • Value prediction for speculative multithreaded architectures 

    Marcuello Pascual, Pedro; Tubella Murgadas, Jordi; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1999)
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    The speculative multithreading paradigm (speculative thread-level parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitectures that adopt this paradigm strongly ...
  • Thread-spawning schemes for speculative multithreading 

    Marcuello Pascual, Pedro; González Colás, Antonio María (IEEE Computer Society, 2002)
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    Speculative multithreading has been recently proposed to boost performance by means of exploiting thread-level parallelism in applications difficult to parallelize. The performance of these processors heavily depends on ...
  • Thermal-aware clustered microarchitectures 

    Chaparro, Pedro; González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2004)
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    As frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it generates are increasing at the same rate. ...
  • Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor 

    Gibert Codina, Enric; Sánchez Navarro, Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2002)
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    Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functional units and the data cache are partitioned, ...
  • Delaying physical register allocation trought virtual-physical registers 

    Monreal Arnal, Teresa; González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 1999)
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    Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This ...
  • A unified modulo scheduling and register allocation technique for clustered processors 

    Codina Viñas, Josep M.; Sánchez Navarro, F. Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2001)
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    This work presents a modulo scheduling framework for clustered ILP processors that integrates the cluster assignment, instruction scheduling and register allocation steps in a single phase. This unified approach is more ...
  • A partial breadth-first execution model for prolog 

    Tubella Murgadas, Jordi; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1994)
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    MEM (Multipath Execution Model) is a novel model for the execution of Prolog programs which combines a depth-first and breadth-first exploration of the search tree. The breadth-first search allows more than one path of the ...
  • Compiler analysis for trace-level speculative multithreaded architectures 

    Molina Clemente, Carlos; González Colás, Antonio María; Tubella Murgadas, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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    Trace-level speculative multithreaded processors exploit trace-level speculation by means of two threads working cooperatively. One thread, called the speculative thread, executes instructions ahead of the other by speculating ...
  • Efficient resources assignment schemes for clustered multithreaded processors 

    Fernando, Latorre; González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2008)
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    New feature sizes provide larger number of transistors per chip that architects could use in order to further exploit instruction level parallelism. However, these technologies bring also new challenges that complicate ...
  • On-line failure detection and confinement in caches 

    Abella Ferrer, Jaume; Chaparro, Pedro; Vera, Xavier; Carretero Casado, Javier Sebastián; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2008)
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    Technology scaling leads to burn-in phase out and increasing post-silicon test complexity, which increases in-the-field error rate due to both latent defects and actual errors. As a consequence, there is an increasing need ...

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