Recent Submissions

  • Branch classification to control instruction fetch in simultaneous multithreaded architectures 

    Knijnenburg, Peter M.W.; Ramírez Bellido, Alejandro; Latorre Salinas, Fernando; Larriba Pey, Josep; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Conference report
    Open Access
    In simultaneous multithreaded architectures many separate threads are running concurrently, sharing processor resources, thereby realizing a high utilization rate of the available hardware. However, this also implies that ...
  • Via-configurable transistors array: a regular design technique to improve ICs yield 

    Pons, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Conference report
    Open Access
    Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ...
  • Virtual registers 

    González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Monreal Arnal, Teresa (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Conference report
    Open Access
    The number of physical registers is one of the critical issues of current superscalar out-of-order processors. Conventional architectures allocate, in the decoding stage, a new storage location (e.g. a physical register) ...
  • From plasma to beefarm: Design experience of an FPGA-based multicore prototype 

    Sonmez, Nehir; Arcas Abella, Oriol; Sayilar, Gokhan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Hur, Ibrahim; Singh, Satnam; Valero Cortés, Mateo (Springer, 2011)
    Conference report
    Open Access
    In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years ...
  • The synergy of multithreading and access/execute decoupling 

    Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/execute decoupling and simultaneous multithreading. We investigate how both techniques complement each other: while ...
  • The Xor embedding: An embedding of hypercubes onto rings and toruses 

    González Colás, Antonio María; Valero García, Miguel (Institute of Electrical and Electronics Engineers (IEEE), 1993)
    Conference report
    Open Access
    Many parallel algorithms use hypercubes as the communication topology among processes, which make them suitable to be executed on a hypercube multicomputer. In this way the communication cost is kept to a minimum since ...
  • Trace-level reuse 

    González Colás, Antonio María; Tubella Murgadas, Jordi; Molina, Carlos (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Conference report
    Open Access
    Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, the instructions that make up such traces ...
  • Trace-level speculative multithreaded architecture 

    Molina Clemente, Carlos; González Colás, Antonio María; Tubella Murgadas, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Conference report
    Open Access
    This paper presents a novel microarchitecture to exploit trace-level speculation by means of two threads working cooperatively in a speculative and non-speculative way respectively. The architecture presents two main ...
  • Speculative dynamic vectorization 

    Pajuelo González, Manuel Alejandro; González Colás, Antonio María; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Conference report
    Open Access
    Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also present in irregular or pointer-rich codes, ...
  • The effectiveness of loop unrolling for modulo scheduling in clustered VLIW architectures 

    Sánchez Navarro, F. Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2000)
    Conference report
    Open Access
    Clustered organizations are becoming a common trend in the design of VLIW architectures. In this work we propose a novel modulo scheduling approach for such architectures. The proposed technique performs the cluster ...

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