Recent Submissions

  • REEM: failure/non-failure region estimation method for SRAM yield analysis 

    Rana, Manish; Canal Corretger, Ramon (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Restricted access - publisher's policy
    The big challenge that we face today for designing resilient memories is the huge number of simulations needed to arrive at a good estimate of memory's yield. A lot of work has come up recently focusing on the reduction ...
  • Framework for economical error recovery in embedded cores 

    Upasani, Gaurang; Vera, Xavier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Restricted access - publisher's policy
    The vulnerability of the current and future processors towards transient errors caused by particle strikes is expected to increase rapidly because of exponential growth rate of on-chip transistors, the lower voltages and ...
  • Accurate off-line phase classification for HW/SW co-designed processors 

    Brankovic, Aleksandar; Stavrou, Kyriakos; Gibert Codina, Enric; González Colás, Antonio María (Association for Computing Machinery (ACM), 2014)
    Conference report
    Open Access
    Evaluation techniques in microprocessor design are mostly based on simulating selected application's samples using a cycle-accurate simulator. These samples usually correspond to different phases of the application stream. ...
  • iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Open Access
    Negative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical ...
  • Variability impact on on-chip memory data paths 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2014)
    Conference lecture
    Open Access
    Process variations have a large impact on device and circuit reliability and performance. Few studies are focused on their impact on more complex systems, as for example their influence in a data path. In our study, the ...
  • FinFET and III-V/Ge technology impact on 3T1D cell behavior 

    Amat Bertran, Esteve; Calomarde Palomino, Antonio; Almudever, Carmen G.; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013)
    Conference lecture
    Open Access
    In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability ...
  • Avoiding core's DUE & SDC via acoustic wave detectors and tailored error containment and recovery 

    Upasani, Gaurang; Vera, Xavier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2014)
    Conference report
    Restricted access - publisher's policy
    The trend of downsizing transistors and operating voltage scaling has made the processor chip more sensitive against radiation phenomena making soft errors an important challenge. New reliability techniques for handling ...
  • Eliminating redundant fragment shader executions on a mobile GPU via hardware memoization 

    Arnau Montañés, José María; Parcerisa Bundó, Joan Manuel; Xekalakis, Polychronis (2014)
    Conference report
    Restricted access - publisher's policy
    Redundancy is at the heart of graphical applications. In fact, generating an animation typically involves the succession of extremely similar images. In terms of rendering these images, this behavior translates into the ...
  • MODEST: a model for energy estimation under spatio-temporal variability 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
    Conference report
    Restricted access - publisher's policy
    Estimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental ...
  • Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability 

    Ganapathy, Shrikanth; Canal Corretger, Ramon; González Colás, Antonio María; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2010)
    Conference report
    Restricted access - publisher's policy
    With every process generation, the problem of variability in physical parameters and environmental conditions poses a great challenge to the design of fast and reliable circuits. Propagation delays which decide circuit ...

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