La principal finalitat del grup és investigar en el camp del disseny arquitectònic dels futurs processadores tenint en compte especialment els nous aspectes tecnològics que el condicionaran, tant per processadors d'alt rendiment com pels destinats a l'electrònica de consum.

El grup continua estant format per la mateixa base de professors doctors que ja vam obtenir l'ajut en les convocatòries SGR tant l'any 2005 com el 2009. Està format per professors del Dpt. d'Arquitectura de Computadors de la UPC juntament amb dos professors de la URV. A aquesta base s'hi ha afegit respecte la darrera convocatòria 4 nous membres doctors amb contracte post-doctoral. La variabilitat cal buscar-la en els membre pre-doctors, on es donen de baixa aquells que ja han acabat la tesi i es donen d'alta els nous estudiants de doctorat.

Volem destacar que el grup ha produït al voltant de 500 articles en congressos i revistes d'alt impacte, més de 100 patents i ha dirigit mes de 25 tesis.

http://futur.upc.edu/ARCO

The mission of the group is to conduct research in the areas of microarchitecture and compilers for future microprocessors. The aim is to increase processors' performance, reduce their energy consumption, improve the effectiveness of heat dissipation, increase their reliability and reduce their complexity.

http://futur.upc.edu/ARCO

The mission of the group is to conduct research in the areas of microarchitecture and compilers for future microprocessors. The aim is to increase processors' performance, reduce their energy consumption, improve the effectiveness of heat dissipation, increase their reliability and reduce their complexity.

http://futur.upc.edu/ARCO

Enviaments recents

  • Performance analysis and optimization of automatic speech recognition 

    Tabani, Hamid; Arnau Montañés, José María; Tubella Murgadas, Jordi; González Colás, Antonio María (2017-08-12)
    Article
    Accés obert
    Fast and accurate Automatic Speech Recognition (ASR) is emerging as a key application for mobile devices. Delivering ASR on such devices is challenging due to the compute-intensive nature of the problem and the power ...
  • Branch classification to control instruction fetch in simultaneous multithreaded architectures 

    Knijnenburg, Peter M.W.; Ramírez Bellido, Alejandro; Latorre Salinas, Fernando; Larriba Pey, Josep; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Text en actes de congrés
    Accés obert
    In simultaneous multithreaded architectures many separate threads are running concurrently, sharing processor resources, thereby realizing a high utilization rate of the available hardware. However, this also implies that ...
  • Via-configurable transistors array: a regular design technique to improve ICs yield 

    Pons, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2007)
    Text en actes de congrés
    Accés obert
    Process variations are a major bottleneck for digital CMOS integrated circuits manufacturability and yield. That is why regular techniques with different degrees of regularity are emerging as possible solutions. Our ...
  • Virtual registers 

    González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Monreal Arnal, Teresa (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Text en actes de congrés
    Accés obert
    The number of physical registers is one of the critical issues of current superscalar out-of-order processors. Conventional architectures allocate, in the decoding stage, a new storage location (e.g. a physical register) ...
  • From plasma to beefarm: Design experience of an FPGA-based multicore prototype 

    Sonmez, Nehir; Arcas Abella, Oriol; Sayilar, Gokhan; Unsal, Osman Sabri; Cristal Kestelman, Adrián; Hur, Ibrahim; Singh, Satnam; Valero Cortés, Mateo (Springer, 2011)
    Text en actes de congrés
    Accés obert
    In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years ...
  • The synergy of multithreading and access/execute decoupling 

    Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Text en actes de congrés
    Accés obert
    This work presents and evaluates a novel processor microarchitecture which combines two paradigms: access/execute decoupling and simultaneous multithreading. We investigate how both techniques complement each other: while ...
  • The Xor embedding: An embedding of hypercubes onto rings and toruses 

    González Colás, Antonio María; Valero García, Miguel (Institute of Electrical and Electronics Engineers (IEEE), 1993)
    Text en actes de congrés
    Accés obert
    Many parallel algorithms use hypercubes as the communication topology among processes, which make them suitable to be executed on a hypercube multicomputer. In this way the communication cost is kept to a minimum since ...
  • Trace-level reuse 

    González Colás, Antonio María; Tubella Murgadas, Jordi; Molina, Carlos (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Text en actes de congrés
    Accés obert
    Trace-level reuse is based on the observation that some traces (dynamic sequences of instructions) are frequently repeated during the execution of a program, and in many cases, the instructions that make up such traces ...
  • Trace-level speculative multithreaded architecture 

    Molina Clemente, Carlos; González Colás, Antonio María; Tubella Murgadas, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Text en actes de congrés
    Accés obert
    This paper presents a novel microarchitecture to exploit trace-level speculation by means of two threads working cooperatively in a speculative and non-speculative way respectively. The architecture presents two main ...
  • Speculative dynamic vectorization 

    Pajuelo González, Manuel Alejandro; González Colás, Antonio María; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Text en actes de congrés
    Accés obert
    Traditional vector architectures have shown to be very effective for regular codes where the compiler can detect data-level parallelism. However, this SIMD parallelism is also present in irregular or pointer-rich codes, ...

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