La principal finalitat del grup és investigar en el camp del disseny arquitectònic dels futurs processadores tenint en compte especialment els nous aspectes tecnològics que el condicionaran, tant per processadors d'alt rendiment com pels destinats a l'electrònica de consum.

El grup continua estant format per la mateixa base de professors doctors que ja vam obtenir l'ajut en les convocatòries SGR tant l'any 2005 com el 2009. Està format per professors del Dpt. d'Arquitectura de Computadors de la UPC juntament amb dos professors de la URV. A aquesta base s'hi ha afegit respecte la darrera convocatòria 4 nous membres doctors amb contracte post-doctoral. La variabilitat cal buscar-la en els membre pre-doctors, on es donen de baixa aquells que ja han acabat la tesi i es donen d'alta els nous estudiants de doctorat.

Volem destacar que el grup ha produït al voltant de 500 articles en congressos i revistes d'alt impacte, més de 100 patents i ha dirigit mes de 25 tesis.

http://futur.upc.edu/ARCO

The mission of the group is to conduct research in the areas of microarchitecture and compilers for future microprocessors. The aim is to increase processors' performance, reduce their energy consumption, improve the effectiveness of heat dissipation, increase their reliability and reduce their complexity.

http://futur.upc.edu/ARCO

The mission of the group is to conduct research in the areas of microarchitecture and compilers for future microprocessors. The aim is to increase processors' performance, reduce their energy consumption, improve the effectiveness of heat dissipation, increase their reliability and reduce their complexity.

http://futur.upc.edu/ARCO

Enviaments recents

  • Quantitative characterization of the software layer of a HW/SW co-designed processor 

    Cano Reyes, José; Kumar, Rakesh; Brankovic, Aleksandar; Pavlou, Demos; Stavrou, Kyriakos; Gibert Codina, Enric; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés obert
    HW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary ...
  • Low-complexity distributed issue queue 

    Abella Ferrer, Jaume; González Colás, Antonio María (IEEE Computer Society, 2004)
    Text en actes de congrés
    Accés obert
    As technology evolves, power density significantly increases and cooling systems become more complex and expensive. The issue logic is one of the processor hotspots and, at the same time, its latency is crucial for the ...
  • Leveraging register windows to reduce physical registers to the bare minimum 

    Quiñones Moreno, Eduardo; Parcerisa Bundó, Joan Manuel; González Colás, Antonio María (2010-12)
    Article
    Accés obert
    Register window is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register requirements ...
  • Late allocation and early release of physical registers 

    Monreal Arnal, Teresa; Viñals Yufera, Víctor; González González, José; González Colás, Antonio María; Valero Cortés, Mateo (2004-10)
    Article
    Accés obert
    The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the ...
  • A detailed methodology to compute soft error rates in advanced technologies 

    Riera Villanueva, Marc; Canal Corretger, Ramon; Abella, Jaume; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    System reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the ...
  • Parsar: parallelisation of a chirp scaling algorithm sar processor 

    MARTINEZ, A; Fraile, F; Mallorquí Franquet, Jordi Joan; Nogueira, J; Gabalda, J; Broquetas Ibars, Antoni; González Colás, Antonio María (1997-08)
    Article
    Accés restringit per política de l'editorial
    A parallel SAR processor is presented in this paper. The target configuration is a cluster of UNIX workstations, available in most user sites. This fact allows to obtain an increased computing performance without the need ...
  • Scalability of broadcast performance in wireless network-on-chip 

    Abadal Cavallé, Sergi; Mestres Sugrañes, Albert; Nemirovsky, Mario; Lee, Heekwan; González Colás, Antonio María; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2016-12-01)
    Article
    Accés obert
    Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors ...
  • Instruction replication for clustered microarchitectures 

    Aleta Ortega, Alexandre; Codina Viñas, Josep M.; González Colás, Antonio María; David, Kaeli (Institute of Electrical and Electronics Engineers (IEEE), 2003)
    Text en actes de congrés
    Accés obert
    This work presents a new compilation technique that uses instruction replication in order to reduce the number of communications executed on a clustered microarchitecture. For such architectures, the need to communicate ...
  • Analysis and optimization of engines for dynamically typed languages 

    Dot Artigas, Gem; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Dynamically typed programming languages have become very popular in the recent years. These languages ease the task of the programmer but introduce significant overheads since assumptions about the types of variables have ...
  • MASkIt: soft error rate estimation for combinatorial circuits 

    Anglada Sánchez, Martí; Canal Corretger, Ramon; Aragon, Juan Luis; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Integrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation ...

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