Exploració per autor "Moll Echeto, Francisco de Borja"
Ara es mostren els items 39-58 de 98
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Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study
(IEEE Computer Society Publications, 2011)
Comunicació de congrés
Accés restringit per política de l'editorialTime-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ... -
Final Exam. Part 1
(Universitat Politècnica de Catalunya, 2021-01-12)
Examen
Accés restringit a la comunitat UPC -
FOCSI: A new layout regularity metric
(2009-06-09)
Report de recerca
Accés obertDigital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ... -
Influència de les Interconnexions en Disseny Microelectrònic
(Universitat Politècnica de Catalunya, 1995-03-31)
Tesi
Accés obertDebido a los actuales niveles de integración que permite la tecnología de fabricación de circuitos integrados, las interconexiones juegan cada vez un papel más importante en el comportamiento de dichos circuitos introduciendo ... -
Insights into tunnel FET-based charge pumps and rectifiers for energy harvesting applications
(2017-03-01)
Article
Accés obertIn this paper, the electrical characteristics of tunnel field-effect transistor (TFET) devices are explored for energy harvesting front-end circuits with ultralow power consumption. Compared with conventional thermionic ... -
Introduction to VHDL I
(2020-09-22)
Audiovisual
Accés obert -
Introduction to VHDL II
(2020-09-22)
Audiovisual
Accés obert -
Introduction to VHDL III
(2020-09-22)
Audiovisual
Accés obert -
Introduction to VHDL IV
(2020-09-22)
Audiovisual
Accés obert -
Introduction to VHDL V
(2020-09-22)
Audiovisual
Accés obert -
Introduction to VHDL VI
(2020-09-22)
Audiovisual
Accés obert -
Introduction to VHDL VII
(2020-09-22)
Audiovisual
Accés obert -
Introduction to VHDL VIII
(2020-09-22)
Audiovisual
Accés obert -
Linear, time-invariant model of the dynamics of a CMOS CC-CP
(Institute of Electrical and Electronics Engineers (IEEE), 2019)
Comunicació de congrés
Accés obertThis paper presents the development of a linear dynamic model of a MOS Cross Coupled Charge Pump (CC-CP) suitable for low voltage energy harvesting systems in the form of a Discrete-Time State-Space set of equations ... -
Lithography aware regular cell design based on a predictive technology model
(2010-12)
Article
Accés restringit per política de l'editorialAs semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ... -
Lithography aware regular cell design based on a predictive technology model
(2010)
Text en actes de congrés
Accés obertAs semiconductor technology advances into the nanoscale era, optical effects such as channel narrowing, corner rounding or line-end pullback are critical to accomplish circuit yield specifications. It is well-demonstrated ... -
Lithography parametric yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
(2014-07-01)
Article
Accés obertA lithography parametric yield estimation model is presented to evaluate the lithography distortion in a printed layout due to lithography hotspots. The aim of the proposed yield model is to provide a new metric that enables ... -
Local variations compensation with DLL-based body bias generator for UTBB FD-SOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialLocal variations are increasingly important in new technologies. This paper presents the design of adaptive circuits based on the concept of Adaptive Body Bias Islands and a Forward and Reverse Body Bias Generator for FDSOI ... -
Logic synthesis for manufacturability considering regularity and lithography printability
(IEEE Computer Society Publications, 2013)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper presents a novel yield model for integrated circuits manufacturing, considering lithography printability problems as a source of yield loss. The use of regular layouts can improve the printability of IC layouts, ... -
Measurements of process variability in 40-nm regular and nonregular layouts
(2014-02-01)
Article
Accés restringit per política de l'editorialAs technology scales down, IC design is becoming more difficult due to the increase in process variations, which translates into a dispersion of circuit parameter values thus degrading manufacturing yield. Regular layouts ...
