Exploració per autor "Martorell Bofill, Xavier"
Ara es mostren els items 44-63 de 140
-
Employing nested OpenMP for the parallelization of multi-zone computational fluid dynamics applications
(2006-05)
Article
Accés restringit per política de l'editorialIn this paper we describe the parallelization of the multi-zone code versions of the NAS Parallel Benchmarks employing multi-level OpenMP parallelism. For our study, we use the NanosCompiler that supports nesting of OpenMP ... -
Enabling HW-based task scheduling in large multicore architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2024-01)
Article
Accés obertDynamic Task Scheduling is an enticing programming model aiming to ease the development of parallel programs with intrinsically irregular or data-dependent parallelism. The performance of such solutions relies on the ability ... -
Energy optimizing methodologies on heterogeneous data centers
(Barcelona Supercomputing Center, 2017-05-04)
Text en actes de congrés
Accés obertIn 2013, U.S. data centers accounted for 2.2% of the country’s total electricity consumption, a figure that is projected to increase rapidly over the next decade. Many important work-loads are interactive, and they demand ... -
ETP4HPC’s SRA 5 strategic research agenda for High-Performance Computing in Europe 2022: European HPC research priorities 2023-2027
(2022-09)
Report de recerca
Accés obertThis document feeds research and development priorities devel-oped by the European HPC ecosystem into EuroHPC’s Research and Innovation Advisory Group with an aim to define the HPC Technology research Work Programme and ... -
Evaluating the impact of OpenMP 4.0 extensions on relevant parallel workloads
(Springer, 2015)
Text en actes de congrés
Accés obertOpenMP has been for many years the most widely used programming model for shared memory architectures. Periodically, new features are proposed and some of them are finally selected for inclusion in the OpenMP standard. The ... -
Evaluation of memory performance on the cell BE with the SARC programming model
(Association for Computing Machinery (ACM), 2008)
Comunicació de congrés
Accés restringit per política de l'editorialWith the advent of multicore architectures, especially with the heterogeneous ones, both computational and memory top performance are difficult to obtain using traditional programming models. Usually, programmers have to ... -
Evaluation of OpenMP for the Cyclops multithreaded architecture
(2003-06)
Article
Accés obertMultithreaded architectures have the potential of tolerating large memory and functional unit latencies and increase resource utilization. The Blue Gene/Cyclops architecture, being developed at the IBM T. J. Watson Research ... -
Experiences parallelizing a web server with OpenMP
(2008)
Article
Accés obertMulti-threaded web servers are typically parallelized by hand using the pthreads library. OpenMP has rarely been used to parallelize such kind of applications, although we foresee that it can be a great tool for network ... -
Exploiting pipelined executions in OpenMP
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertWe propose a set of extensions to the OpenMP programming model to express point-to-point synchronisation schemes. This is accomplished by defining, in the form of directives, precedence relations among the tasks that are ... -
Extending OmpSs for OpenCL kernel co-execution in heterogeneous systems
(Institute of Electrical and Electronics Engineers (IEEE), 2017)
Text en actes de congrés
Accés obertHeterogeneous systems have a very high potential performance but present difficulties in their programming. OmpSs is a well known framework for task based parallel applications, which is an interesting tool to simplify the ... -
Extending OpenMP to survive the heterogeneous multi-core era
(2010-10)
Article
Accés restringit per política de l'editorial -
Extending OpenMP* with vector constructs for modern multicore SIMD architectures
(Springer, 2012)
Text en actes de congrés
Accés restringit per política de l'editorialIn order to obtain maximum performance, many applications require to extend parallelism from multi-threading to instruction-level (SIMD) parallelism that exists in many current (and future) multi-core architectures. While ... -
Fast evaluation methodology for automatic custom hardware prototyping
(2009-06)
Text en actes de congrés
Accés obertHardware customization for scientific applications has shown a big potential for reducing power consumption and increasing performance. In particular, the automatic generation of ISA extensions for General-Purpose Processors ... -
Fine-grain parallel megabase sequence comparison with multiple heterogeneous GPUs
(Association for Computing Machinery (ACM), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper proposes and evaluates a parallel strategy to execute the exact Smith-Waterman (SW) algorithm for megabase DNA sequences in heterogeneous multi-GPU platforms. In our strategy, the computation of a single huge ... -
Fine-grain parallel megabase sequence comparison with multiple heterogeneous GPUs
(2014-08-01)
Article
Accés restringit per política de l'editorialThis paper proposes and evaluates a parallel strategy to execute the exact Smith-Waterman (SW) algorithm for megabase DNA sequences in heterogeneous multi-GPU platforms. In our strategy, the computation of a single huge ... -
Formalization of block pruning: reducing the number of cells computed in exact biological sequence comparison algorithms
(Wiley Heyden, 2018-05-01)
Article
Accés obertBiological sequence comparison algorithms that compute the optimal local and global alignments calculate a dynamic programming (DP) matrix with quadratic time complexity. The DP matrix H is calculated with a recurrence ... -
FPGA framework improvements for HPC applications
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertIn modern FPGA devices, place and route has become an increasingly difficult task due to an increase in resources and device complexity. This results in an exponential increase of implementation possibilities. Such a huge ... -
Hardware-software coherence protocol for the coexistence of caches and local memories
(2015-01-01)
Article
Accés obertCache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce ... -
HBM, present and future of HPC based on FPGAs
(Barcelona Supercomputing Center, 2022-05)
Text en actes de congrés
Accés obertIn the past decades, advances in the speed of commodity CPUs have far out-paced advances in memory latency. Mainmemory access is therefore increasingly a performance bottleneck for many computer applications, including HPC ... -
Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialOmpSs is a directive-based programming model that uses OpenMP-like directives, that allow to execute the tasks annotated on both the SMPs and as FPGA kernels on modern SoC processors, like the Xilinx Zynq platform. OmpSs ...
