Show simple item record

dc.contributor.authorTabani, Hamid
dc.contributor.authorArnau Montañés, José María
dc.contributor.authorTubella Murgadas, Jordi
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2018-10-11T14:41:14Z
dc.date.issued2018
dc.identifier.citationTabani, H., Arnau, J., Tubella, J., Gonzalez Colas, A. A novel register renaming technique for out-of-order processors. A: International Symposium on High-Performance Computer Architecture. "2018 IEEE International Symposium on High Performance Computer Architecture (HPCA 2018): Vienna, Austria; 24-28 February 2018". Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 259-270.
dc.identifier.isbn978-1-5386-3660-2
dc.identifier.urihttp://hdl.handle.net/2117/122264
dc.description.abstractModern superscalar processors support a large number of in-flight instructions, which requires sizeable register files. Conventional register renaming techniques allocate a new storage location, i.e. physical register, for every instruction whose destination is a logical register in order to remove false dependences. Physical registers are released in a conservative manner when the same logical register is redefined. For this reason, many cycles may happen between the last read and the release of a physical register, leading to suboptimal utilization of the register file. We have observed that for more than 50% of the instructions in SPECfp and more than 30% of the instructions in SPECint that have a destination register, the produced value has only a single consumer. In this case, the RAW dependence guarantees that the producer-consumer instructions pair will be executed in program order and, hence, the same physical register can be used to store the value produced by both instructions. In this paper, we propose a renaming technique that exploits this property to reduce the pressure on the register file. Our technique leverages physical register sharing by introducing minor changes in the register map table and the issue queue. We also describe how our renaming scheme supports precise exceptions. We evaluated our renaming technique on top of a modern out-of-order processor. Our experimental results show that it provides 6% speedup on average for the SPEC2006 benchmarks. Alternatively, our renaming scheme achieves the same performance while reducing the number of physical registers by 10.5%.
dc.format.extent12 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors::Arquitectures paral·leles
dc.subject.lcshHigh performance computing
dc.subject.otherPrecise exceptions
dc.subject.otherRegister file
dc.subject.otherRegister renaming supercomputers
dc.subject.otherIn-flight instructions
dc.subject.otherOut-of-order processors
dc.subject.otherPhysical registers
dc.subject.otherPrecise exceptions
dc.subject.otherProducer consumers
dc.subject.otherRegister files
dc.subject.otherRegister renaming
dc.subject.otherSuperscalar processor
dc.subject.otherComputer architecture
dc.titleA novel register renaming technique for out-of-order processors
dc.typeConference report
dc.subject.lemacCàlcul intensiu (Informàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.contributor.groupUniversitat Politècnica de Catalunya. CERCLE - Cercle d'Arquitectura
dc.identifier.doi10.1109/HPCA.2018.00031
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttps://ieeexplore.ieee.org/document/8327014
dc.rights.accessRestricted access - publisher's policy
local.identifier.drac23408725
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO//TIN2013-44375-R/ES/MICROARQUITECTURA Y COMPILADORES PARA FUTUROS PROCESADORES III/
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TIN2016-75344-R
dc.date.lift10000-01-01
local.citation.authorTabani, H.; Arnau, J.; Tubella, J.; Gonzalez Colas, A.
local.citation.contributorInternational Symposium on High-Performance Computer Architecture
local.citation.publicationName2018 IEEE International Symposium on High Performance Computer Architecture (HPCA 2018): Vienna, Austria; 24-28 February 2018
local.citation.startingPage259
local.citation.endingPage270


Files in this item

Thumbnail

This item appears in the following Collection(s)

Show simple item record