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Synthesis of IDDQ-Testable Circuits: Integrating Built-in Current Sensors
(1995)
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"On-Chip" I_{DDQ} testing by the incorporation of Built-In Current (BIC) sensors has some advantages over "off-chip" techniques. However, the integration of sensors poses analog design problems which are hard to be solved ...
Differential scan-path: A novel solution for secure design-for-testability
(2013)
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In this paper, we present a new scan-path structure for improving the security of systems including scan paths, which normally introduce a security critical information leak channel into a design. Our structure, named ...
Diagnosis of full open defects in interconnecting lines
(IEEE, 2007-05-31)
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A proposal for enhancing the diagnosis of full open defects in interconnecting lines of CMOS circuits is presented. The defective line is first classified as fully opened by means of a logic-based diagnosis tool (Faloc). ...
Information Leakage Reduction at the Scan-Path Output
(2013)
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In this paper we present a new scan-path structure for improving the security of systems including a scan path, which normally introduces a security critical information channel into a design. The structure, named differential ...
Diagnosis of full open defects in interconnect lines with fan-out
(IEEE Press. Institute of Electrical and Electronics Engineers, 2010-05-24)
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The development of accurate diagnosis
methodologies is important to solve process problems and achieve fast yield improvement. As open defects are common in CMOS
technologies, accurate diagnosis of open defects becomes ...
Post-Bond test of through-silicon vias with open defects
(2014)
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Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs) and are susceptible to undergo defects at different stages: during their own fabrication, the bonding stage or during ...
BIST Architecture to Detect Defects in TSVs During Pre-Bond Testing
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
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Through Silicon Vias (TSVs) are critical elements in three dimensional integrated circuits (3-D ICs). The detection of defective TSVs in the earliest process step is of major concern. Hence, testing TSVs is usually done ...