A cache design for probabilistically analysable real-time systems
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Caches provide significant performance improvements, though their use in real-time industry is low because current WCET analysis tools require detailed knowledge of program's cache accesses to provide tight WCET estimates. Probabilistic Timing Analysis (PTA) has emerged as a solution to reduce the amount of information needed to provide tight WCET estimates, although it imposes new requirements on hardware design. At cache level, so far only fully-associative random-replacement caches have been proven to fulfill the needs of PTA, but they are expensive in size and energy. In this paper we propose a cache design that allows setassociative and direct-mapped caches to be analysed with PTA techniques. In particular we propose a novel parametric random placement suitable for PTA that is proven to have low hardware complexity and energy consumption while providing comparable performance to that of conventional modulo placement.
CitacióKosmidis, L. [et al.]. A cache design for probabilistically analysable real-time systems. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe: Grenoble, France, March 18 - 22, 2013". Grenoble: 2013, p. 513-518.
Versió de l'editorhttp://dl.acm.org/citation.cfm?id=2485288.2485416
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