Enviaments recents

  • Parsar: parallelisation of a chirp scaling algorithm sar processor 

    MARTINEZ, A; Fraile, F; Mallorquí Franquet, Jordi Joan; Nogueira, J; Gabalda, J; Broquetas Ibars, Antoni; González Colás, Antonio María (1997-08)
    Article
    Accés restringit per política de l'editorial
    A parallel SAR processor is presented in this paper. The target configuration is a cluster of UNIX workstations, available in most user sites. This fact allows to obtain an increased computing performance without the need ...
  • Scalability of broadcast performance in wireless network-on-chip 

    Abadal Cavallé, Sergi; Mestres Sugrañes, Albert; Nemirovsky, Mario; Lee, Heekwan; González Colás, Antonio María; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2016-12-01)
    Article
    Accés obert
    Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors ...
  • Securely-entrusted multi-topology routing for community networks 

    Neumann, Axel; López Berga, Ester; Cerdà Alabern, Llorenç; Navarro Moldes, Leandro (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Routing in open and decentralized networks relies on coopera- tion despite the participation of unknown (alien) nodes and node administrators pursuing heterogeneous trust and security goals. Living use cases for such ...
  • Echo state hoeffding tree learning 

    Marron Vida, Diego; Read, Jesse; Bifet, Albert; Abdessalem, Talel; Ayguadé Parra, Eduard; Herrero Zaragoza, José Ramón (Microtome Publishing, 2016)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Nowadays, real-time classi cation of Big Data streams is becoming essential in a variety of application domains. While decision trees are powerful and easy{to{deploy approaches for accurate and fast learning from data ...
  • The AXIOM project (Agile, eXtensible, fast I/O Module) 

    Theodoropoulos, Dimitris; Pnevmatikatos, Dionisis; Alvarez, Carlos; Ayguadé Parra, Eduard; Bueno, Javier; Filgueras Izquierdo, Antonio; Jiménez-González, Daniel; Martorell Bofill, Xavier; Navarro, Nacho; Segura, Carlos; Fernandez, Carles; Oro, David; Rodriguez Saeta, Javier; Gai, Paolo; Rizzo, Antonio; Giorgi, Roberto (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    The AXIOM project (Agile, eXtensible, fast I/O Module) aims at researching new software/hardware architectures for the future Cyber-Physical Systems (CPSs). These systems are expected to react in real-time, provide enough ...
  • Large-memory nodes for energy efficient high-performance computing 

    Zivanovic, Darko; Radulovic, Milan; Llort, German; Zaragoza, David; Strassburg, Janko; Carpenter, Paul M.; Radojkovic, Petar; Ayguadé Parra, Eduard (Association for Computing Machinery (ACM), 2016)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Energy consumption is by far the most important contributor to HPC cluster operational costs, and it accounts for a significant share of the total cost of ownership. Advanced energy-saving techniques in HPC components have ...
  • Instruction replication for clustered microarchitectures 

    Aleta Ortega, Alexandre; Codina Viñas, Josep M.; González Colás, Antonio María; David, Kaeli (Institute of Electrical and Electronics Engineers (IEEE), 2003)
    Text en actes de congrés
    Accés obert
    This work presents a new compilation technique that uses instruction replication in order to reduce the number of communications executed on a clustered microarchitecture. For such architectures, the need to communicate ...
  • A structural encoding technique for the synthesis of asynchronous circuits 

    Carmona Vargas, Josep; Cortadella Fortuny, Jordi; Pastor Llorens, Enric (2000-12)
    Report de recerca
    Accés obert
    This paper presents a method for the automatic synthesis of asynchronous circuits from Petri net specifications. The method is based on a structural encoding of the system in such a way that a circuit implementation is ...
  • Analysis and optimization of engines for dynamically typed languages 

    Dot Artigas, Gem; Martínez, Alejandro; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2015)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Dynamically typed programming languages have become very popular in the recent years. These languages ease the task of the programmer but introduce significant overheads since assumptions about the types of variables have ...
  • MASkIt: soft error rate estimation for combinatorial circuits 

    Anglada Sánchez, Martí; Canal Corretger, Ramon; Aragon, Juan Luis; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2016)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Integrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation ...

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