Enviaments recents

  • The MPsim simulation tool 

    Acosta Ojeda, Carmelo Alexis; Cazorla, Francisco; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009)
    Report de recerca
    Accés obert
    In order to evaluate novel ideas, computer architects require simulation tools which model a target architecture. According to the specific accuracy requirements we find very specific simulators, which model a single ...
  • Maximizing multithreaded multicore architectures through thread migrations 

    Acosta Ojeda, Carmelo Alexis; Cazorla Almeida, Francisco Javier; Santana Jaria, Oliverio J.; Falcón Samper, Ayose Jesús; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2009)
    Report de recerca
    Accés obert
    Heterogeneity in general-purpose workloads often end up in non optimal per-thread hardware resource usage. The current trend towards multicore architectures, containing several multithreaded cores, increases the need of a ...
  • A distributed processor state management architecture for large-window processors 

    González, Isidro; Galluzzi, Marco; Veidenbaum, Alexander V.; Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2008)
    Text en actes de congrés
    Accés obert
    Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed architectures replace a re-order buffer (ROB) with ...
  • Performance analysis of sequence alignment applications 

    Sánchez Castaño, Friman; Salamí San Juan, Esther; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2006)
    Text en actes de congrés
    Accés obert
    Advances in molecular biology have led to a continued growth in the biological information generated by the scientific community. Additionally, this area has become a multi-disciplinary field, including components of ...
  • PaaS-IaaS inter-layer adaptation in an energy-aware cloud environment 

    Djemame, Karim; Bosch, Raimon; Kavanagh, Richard; Alvarez, Pol; Ejarque, Jorge; Guitart Fernández, Jordi; Blasi, Lorenzo (Institute of Electrical and Electronics Engineers (IEEE), 2017-06)
    Article
    Accés obert
    Cloud computing providers resort to a variety of techniques to improve energy consumption at each level of the cloud computing stack. Most of these techniques consider resource-level energy optimization at IaaS layer. This ...
  • Do we all really know what a fog node is? Current trends towards an open definition 

    Marín Tordera, Eva; Masip Bruin, Xavier; García Almiñana, Jordi; Jukan, Admela; Ren, Guang-Jie; Zhu, Jiafeng (2017-09-01)
    Article
    Accés obert
    Fog computing has emerged as a promising technology that can bring cloud applications closer to the physical IoT devices at the network edge. While it is widely known what cloud computing is, how data centers can build the ...
  • Resolucion de problemas electromagneticos mediante el metodo de elementos finitos en computadores de paralelismo masivo 

    Cruellas Ibarz, Juan Carlos; Duffo Ubeda, Núria (Universitat Politècnica de València, 1993)
    Text en actes de congrés
    Accés obert
  • Managing resources continuity from the edge to the cloud: Architecture and performance 

    Masip Bruin, Xavier; Marín Tordera, Eva; Jukan, Admela; Ren, Guang-Jie (Elsevier, 2017-01-01)
    Article
    Accés obert
    The wide spread deployment of smart edge devices and applications that require real-time data processing, have with no doubt created the need to extend the reach of cloud computing to the edge, recently also referred to ...
  • A case for merging the ILP and DLP paradigms 

    Quintana Rodríguez, Francisca; Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1998)
    Text en actes de congrés
    Accés obert
    The goal of this paper is to show that instruction level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute vectorizable code at a performance level that can not be achieved ...
  • Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance 

    Espasa Sans, Roger; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 1997)
    Text en actes de congrés
    Accés obert
    Shows that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single simultaneous vector multithreaded architecture to execute regular vectorizable code at a performance level that ...

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