Enviaments recents

  • Modeling seismic wave propagation using staggered-grid mimetic finite differences 

    Solano, Freysimar; Guevara-Jordan, Juan; González, Carlos; Rojas, Otilio; Otero Calviño, Beatriz (2017-04-12)
    Article
    Accés obert
    Mimetic finite difference (MFD) approximations of continuous gradient and divergente operators satisfy a discrete version of the Gauss-Divergente theorem on staggered grids. On the mimetic approximation of this integral ...
  • OrthoNoC: a broadcast-oriented dual-plane wireless network-on-chip architecture 

    Abadal Cavallé, Sergi; Torrellas Jovani, Josep; Alarcón Cot, Eduardo José; Cabellos Aparicio, Alberto (2017-10-20)
    Article
    Accés obert
    On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater ...
  • Non-consistent dual register files to reduce register pressure 

    Llosa Espuny, José Francisco; Valero Cortés, Mateo; Ayguadé Parra, Eduard (Institute of Electrical and Electronics Engineers (IEEE), 1995)
    Text en actes de congrés
    Accés obert
    The continuous grow on instruction level parallelism offered by microprocessors requires a large register file and a large number of ports to access it. This paper presents the non-consistent dual register file, an alternative ...
  • Scalable topological forwarding and routing policies in RINA-enabled programmable data centers 

    Leon Gaixas, Sergio; Perelló Muntan, Jordi; Careglio, Davide; Grasa, Eduard; Lopez, Diego; Aranda Gutiérrez, Pedro Andrés (Wiley-Blackwell, 2017-11-19)
    Article
    Accés restringit per política de l'editorial
    Given the current expansion of cloud computing, the expected advent of the Internet of Things, and the requirements of future fifth-generation network infrastructures, significantly larger pools of computational and storage ...
  • Cognitive science applied to reduce network operation margins 

    Notivol Calleja, Luis David; Spadaro, Salvatore; Perelló Muntan, Jordi; Junyent Giralt, Gabriel (2017-06-08)
    Article
    Accés restringit per política de l'editorial
    In an increasingly competitive market environment with smaller product offer differentiation, a continuous maximization of efficiency, while guarantying the quality of the provided services, remains a main objective for ...
  • Evaluating the benefits of combined and continuous Fog-to-Cloud architectures 

    Ramirez Almonte, Wilson; Masip Bruin, Xavier; Marín Tordera, Eva; Barbosa Carlos de Souza, Vitor; Jukan, Admela; Ren, Guang-Jie; González de Dios, Oscar (2017-11-15)
    Article
    Accés obert
    The need to extend the features of Cloud computing to the edge of the network has fueled the development of new computing architectures, such as Fog computing. When put together, the combined and continuous use of fog and ...
  • Out-of-order commit processors 

    Cristal Kestelman, Adrián; Ortega, Daniel; Llosa Espuny, José Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    Modern out-of-order processors tolerate long latency memory operations by supporting a large number of in-flight instructions. This is particularly useful in numerical applications where branch speculation is normally not ...
  • Direct instruction wakeup for out-of-order processors 

    Ramírez, Marco Antonio; Cristal Kestelman, Adrián; Veidenbaum, Alex; Villa, Luis A; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    Instruction queues consume a significant amount of power in high-performance processors, primarily due to instruction wakeup logic access to the queue structures. The wakeup logic delay is also a critical timing parameter. ...
  • A conflict-free memory banking architecture for fast VOQ packet buffers 

    García Vidal, Jorge; Cerdà Alabern, Llorenç; Corbal San Adrián, Jesús; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2003)
    Text en actes de congrés
    Accés obert
    In order to support the enormous growth of the Internet, innovative research in every router subsystem is needed. We focus our attention on packet buffer design for routers supporting high-speed line rates. More specifically, ...
  • SEDEA: A sensible approach to account DRAM energy in multicore systems 

    Liu, Qixiao; Moreto Planas, Miquel; Abella, Jaume; Cazorla, Francisco; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés obert
    As the energy cost in todays computing systems keeps increasing, measuring the energy becomes crucial in many scenarios. For instance, due to the fact that the operational cost of datacenters largely depends on the energy ...
  • On the design of hybrid DRAM/SRAM memory schemes for fast packet buffers 

    García Vidal, Jorge; March Hermo, María Isabel; Cerdà Alabern, Llorenç; Corbal San Adrián, Jesús; Valero Cortés, Mateo (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    We address the design of a packet buffer for future high-speed routers that support line rates as high as OC-3072 (160 Gb/s), and a high number of ports and service classes. We describe a general design for hybrid DRAM/SRAM ...
  • Dynamic virtual network connectivity for C-RAN backhauling 

    Asensio Garcia, Adrian; Ruiz Ramírez, Marc; Velasco Esteban, Luis Domingo (Institute of Electrical and Electronics Engineers (IEEE), 2017)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Aiming at satisfying in a cost-effective manner the forecast traffic growth that future mobile networks will need to support, traditional distributed Radio Access Networks (RANs) are evolving towards centralized ...

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