Enviaments recents

  • Measurement-based timing analysis of the AURIX caches 

    Kosmidis, Leonidas; Compagnin, Davide; Morales, David; Mezzetti, Enrico; Quiñones Moreno, Eduardo; Abella Ferrer, Jaume; Vardanega, Tullio; Cazorla Almeida, Francisco Javier (Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
    Text en actes de congrés
    Accés obert
    Cache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has ...
  • A distributed power sharing framework among households in microgrids: a repeated game approach 

    Alskaif, Tarek; Guerrero Zapata, Manel; Bellalta Jimenez, Boris; Nilsson, Anders (2017-01-01)
    Article
    Accés restringit per política de l'editorial
    In microgrids, the integration of distributed energy resources (DERs) in the residential sector can improve power reliability, and potentially reduce power demands and carbon emissions. Improving the utilization of renewable ...
  • Value prediction for speculative multithreaded architectures 

    Marcuello Pascual, Pedro; Tubella Murgadas, Jordi; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Text en actes de congrés
    Accés obert
    The speculative multithreading paradigm (speculative thread-level parallelism) is based on the concurrent execution of control-speculative threads. The efficiency of microarchitectures that adopt this paradigm strongly ...
  • Thread-spawning schemes for speculative multithreading 

    Marcuello Pascual, Pedro; González Colás, Antonio María (IEEE Computer Society, 2002)
    Text en actes de congrés
    Accés obert
    Speculative multithreading has been recently proposed to boost performance by means of exploiting thread-level parallelism in applications difficult to parallelize. The performance of these processors heavily depends on ...
  • Thread partitioning and value prediction for exploiting speculative thread-level parallelism 

    Marcuello, Pedro; González Colás, Antonio María; Tubella Murgadas, Jordi (2004-02)
    Article
    Accés obert
    Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model ...
  • Thermal-aware clustered microarchitectures 

    Chaparro, Pedro; González González, José; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2004)
    Text en actes de congrés
    Accés obert
    As frequencies and feature size scale faster than operating voltages, power density is increasing in each processor generation. Power density and the cost of removing the heat it generates are increasing at the same rate. ...
  • Understanding the thermal implications of multicore architectures 

    Chaparro, Pedro; González González, José; Magklis, Grigorios; Cai, Qiong; González Colás, Antonio María (2007-08)
    Article
    Accés obert
    Multicore architectures are becoming the main design paradigm for current and future processors. The main reason is that multicore designs provide an effective way of overcoming instruction-level parallelism (ILP) limitations ...
  • Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor 

    Gibert Codina, Enric; Sánchez Navarro, Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2002)
    Text en actes de congrés
    Accés obert
    Clustering is a common technique to overcome the wire delay problem incurred by the evolution of technology. Fully-distributed architectures, where the register file, the functional units and the data cache are partitioned, ...
  • Delaying physical register allocation trought virtual-physical registers 

    Monreal Arnal, Teresa; González Colás, Antonio María; Valero Cortés, Mateo; González González, José; Viñals Yufera, Víctor (Institute of Electrical and Electronics Engineers (IEEE), 1999)
    Text en actes de congrés
    Accés obert
    Register file access time represents one of the critical delays of current microprocessors, and it is expected to become more critical as future processors increase the instruction window size and the issue width. This ...
  • A unified modulo scheduling and register allocation technique for clustered processors 

    Codina Viñas, Josep M.; Sánchez Navarro, F. Jesús; González Colás, Antonio María (Institute of Electrical and Electronics Engineers (IEEE), 2001)
    Text en actes de congrés
    Accés obert
    This work presents a modulo scheduling framework for clustered ILP processors that integrates the cluster assignment, instruction scheduling and register allocation steps in a single phase. This unified approach is more ...

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