Interconnecting lines with full open defects become floating lines. In nanometric CMOS technologies, gate tunnelling leakage currents impact the behaviour of these lines, which cannot be considered
electrically isolated anymore. The voltage of the floating node is determined by its neighbours and leakage currents. After some time an equilibrium is reached between these effects. Theoretical analysis and experimental evidence of this behaviour are presented.
Electronics Letter of the Month
CitationRodriguez, R. [et al.]. Impact of gate tunnelling leakage on CMOS circuits with full open defects. "Electronics Letters", Octubre 2007, vol. 43, núm. Issue 21, p. 1140-1141.
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