Exploració per autor "Cristal Kestelman, Adrián"
Ara es mostren els items 101-120 de 129
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RETHINK big: European roadmap for hardware anc networking optimizations for big data
(Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
Comunicació de congrés
Accés obertThis paper discusses the results of the RETHINK big Project, a 2-year Collaborative Support Action funded by the European Commission in order to write the European Roadmap for Hardware and Networking optimizations for Big ... -
ROB-free architecture proposal
(2007-09)
Report de recerca
Accés obertModern processors improve performance by taking advantage of the instruction level parallelism (ILP) by means of allowing hundreds of instructions in flight. However, they still have to face an important source of degradation ... -
Runtime-aware architectures
(Springer, 2015)
Text en actes de congrés
Accés obertIn the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software ... -
Sargantana: an academic SoC RISC-V processor in 22nm FDSOI technology
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertThis paper describes the Sargantana System on chip (SoC), a 64-bit RISC-V single core processor designed by a number of academic institutions and manufactured in 22 nm FDSOI technology: BSC, UPC, UB, UAB, CIC-IPN and IMB-CNM ... -
Solving multiprocessor drawbacks with kilo-instruction processors
(2005)
Report de recerca
Accés obertNowadays, a good multiprocessor system design has to deal with many drawbacks in order to achieve a good tradeoff between complexity and performance. For example, while solving problems like coherence and consistency is ... -
Spatial support vector regression to detect silent errors in the exascale era
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertAs the exascale era approaches, the increasing capacity of high-performance computing (HPC) systems with targeted power and energy budget goals introduces significant challenges in reliability. Silent data corruptions ... -
Stand-alone memory controller for graphics system
(Springer, 2014)
Text en actes de congrés
Accés restringit per política de l'editorialThere has been a dramatic increase in the complexity of graphics applications in System-on-Chip (SoC) with a corresponding increase in performance requirements. Various powerful and expensive platforms to support graphical ... -
Supporting stateful tasks in a dataflow graph
(Association for Computing Machinery (ACM), 2012)
Text en actes de congrés
Accés restringit per política de l'editorialThis paper introduces Atomic Dataflow Model (ADF) - a programming model for shared-memory systems that combines aspects of dataflow programming with the use of explicitly mutable state. The model provides language ... -
System-level power & energy estimation methodology and optimization techniques for CPU-GPU based mobile platforms
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Text en actes de congrés
Accés restringit per política de l'editorialDue to the growing computational requirements of mobile applications, using a heterogeneous Multiprocessor System-on-Chip becomes an incontrovertible solution to meet the service requirements. Today, Electronic System-Level ... -
TauRieL: targeting Traveling Salesman Problem with deep reinforcement learning
(Barcelona Supercomputing Center, 2019-05-07)
Text en actes de congrés
Accés obert -
The MS-processor's register file timing and power evaluation
(2008-09)
Report de recerca
Accés obertPower evaluation is an important issue in new proposal chip level architectures due to the big amount of power is dissipated as head and chips have limited head dissipation capacity. The evaluation shown in this technical ... -
The velox transactional memory stack
(2010-09)
Article
Accés obertThe transactional memory programming paradigm could become the coordination methodology of choice for actual and future multicore and many-core architectures. The transactional memory support spans a complete software and ... -
TM-dietlibc: A TM-aware real-world system library
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialThe simplicity of concurrent programming with Transactional Memory (TM) and its recent implementation in mainstream processors greatly motivates researchers and industry to investigate this field and propose new implementations ... -
Towards fair, scalable, locking
(2008)
Text en actes de congrés
Accés obertWithout care, Hardware Transactional Memory presents several performance pathologies that can degrade its performance. Among them, writers of commonly read variables can suffer from starvation. Though different solutions ... -
Towards zero-waste recovery and zero-overhead checkpointing in ensemble data assimilation
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertEnsemble data assimilation is a powerful tool for increasing the accuracy of climatological states. It is based on combining observations with the results from numerical model simulations. The method comprises two steps, ... -
Transaction processing core for accelerating software transactional memory
(2007-08)
Report de recerca
Accés obertThis paper introduces an advanced hardware based approach for accelerating Software Transactional Memory (STM). The proposed solution focuses on speeding up conflict detection that grows polynomially with the number of ... -
Transactional memory and OpenMp
(2007-06)
Article
Accés restringit per política de l'editorialFuture generations of Chip Multiprocessors (CMP) will provide dozens or even hundreds of cores inside the chip. Writing applications that benefit from the massive computational power offered by these chips is not going to ... -
Transactional memory: an overview
(2007-05)
Article
Accés restringit per política de l'editorialWriting applications that benefit from the massive computational power of future multicore chip multiprocessors will not be an easy task for mainstream programmers accustomed to sequential algorithms rather than parallel ... -
Understanding power consumption and reliability of high-bandwidth memory with voltage underscaling
(Institute of Electrical and Electronics Engineers (IEEE), 2021)
Text en actes de congrés
Accés obertModern computing devices employ High-Bandwidth Memory (HBM) to meet their memory bandwidth requirements. An HBM-enabled device consists of multiple DRAM layers stacked on top of one another next to a compute chip (e.g, ... -
VALib and SimpleVector: Tools for rapid initial research on vector architectures
(Association for Computing Machinery (ACM), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialVector architectures have been traditionally applied to the supercomputing domain with many successful incarnations. The energy efficiency and high performance of vector processors, as well as their applicability in other ...
