Document typeConference report
Rights accessOpen Access
In the last few years, the traditional ways to keep the increase of hardware performance to the rate predicted by the Moore’s Law have vanished. When uni-cores were the norm, hardware design was decoupled from the software stack thanks to a well defined Instruction Set Architecture (ISA). This simple interface allowed developing applications without worrying too much about the underlying hardware, while hardware designers were able to aggressively exploit instruction-level parallelism (ILP) in superscalar processors. Current multi-cores are designed as simple symmetric multiprocessors (SMP) on a chip. However, we believe that this is not enough to overcome all the problems that multi-cores face. The runtime system of the parallel programming model has to drive the design of future multi-cores to overcome the restrictions in terms of power, memory, programmability and resilience that multi-cores have. In the paper, we introduce an approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime’s perspective.
CitationCasas, M., Moreto, M., Álvarez, Ll., Castillo, E., Chasapis, D., Hayes, T., Jaulmes, L., Palomar, Ó., Unsal, O., Cristal, A., Ayguadé, E., Labarta, J., Valero, M. Runtime-aware architectures. A: International European Conference on Parallel and Distributed Computing. "Euro-Par 2015: Parallel Processing: 21st International Conference on Parallel and Distributed Computing, Vienna, Austria, August 24-28, 2015: proceedings". Viena: Springer, 2015, p. 16-27.