Exploració per autor "Canal Corretger, Ramon"
Ara es mostren els items 23-42 de 83
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Effectiveness of hybrid recovery techniques on parametric failures
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialModern day microprocessors effectively utilise supply voltage scaling for tremendous power reduction. The minimum voltage beyond which a processor cannot operate reliably is defined as V ddmin. On-chip memories like caches ... -
Elastic cooperative caching: an autonomus dynamically adaptive memory hierarchy for chip multiprocessors
(Association for Computing Machinery (ACM), 2010)
Text en actes de congrés
Accés restringit per política de l'editorialNext generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of applications with very different memory needs, ... -
Enhancing 3T DRAMs for SRAM replacement under 10nm tri-gate SOI FinFETs
(IEEE Computer Society Publications, 2012)
Text en actes de congrés
Accés restringit per política de l'editorialIn this paper, we pr esent the dynamic 3T memory cell for future 10nm tri-gate FinFETs as a potential replacement for classical 6T SRAM cell for implementation in high speed cache memories. We investigate read access ... -
ETS 2022 ORGANIZING COMMITTEE
(2022-05)
Text en actes de congrés
Accés obert -
Fast and accurate SER estimation for large combinational blocks in early stages of the design
(Institute of Electrical and Electronics Engineers (IEEE), 2021-07-01)
Article
Accés obertSoft Error Rate (SER) estimation is an important challenge for integrated circuits because of the increased vulnerability brought by technology scaling. This paper presents a methodology to estimate in early stages of the ... -
FinFET and III-V/Ge technology impact on 3T1D cell behavior
(2013)
Comunicació de congrés
Accés obertIn this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability ... -
Impact of finfet and III-V/Ge technology on logic and memory cell behavior
(2013-11-20)
Article
Accés restringit per política de l'editorialIn this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ... -
Impact of positive bias temperature instability (PBTI)
(2011)
Text en actes de congrés
Accés restringit per política de l'editorialMemory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure ... -
INFORMER: an integrated framework for early-stage memory robustness analysis
(European Interactive Digital Advertising Alliance (EDAA), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialWith the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware ... -
iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches
(Institute of Electrical and Electronics Engineers (IEEE), 2014)
Text en actes de congrés
Accés obertNegative bias temperature instability (NBTI) is a major cause of concern for chip designers because of its inherent ability to drastically reduce silicon reliability over the lifetime of the processor. Coupled with statistical ... -
Lightning talks of EduHPC 2022
(Institute of Electrical and Electronics Engineers (IEEE), 2022)
Text en actes de congrés
Accés obertThe lightning talks at EduHPC provide an opportunity to share early results and insights on parallel and distributed computing (PDC) education and training efforts. The four lightning talks at EduHPC 2022 cover a range of ... -
Lightweight protection of cryptographic hardware accelerators against differential fault analysis
(Institute of Electrical and Electronics Engineers (IEEE), 2020)
Text en actes de congrés
Accés obertHardware acceleration circuits for cryptographic algorithms are largely deployed in a wide range of products. The HW implementations of such algorithms often suffer from a number of vulnerabilities that expose systems to ... -
Malicious website detection through deep learning algorithms
(Springer Nature, 2022)
Text en actes de congrés
Accés obertTraditional methods that detect malicious websites, such as blacklists, do not update frequently, and they cannot detect new attackers. A system capable of detecting malicious activity using Deep Learning (DL) has been ... -
MASkIt: soft error rate estimation for combinatorial circuits
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés restringit per política de l'editorialIntegrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation ... -
MeRLiN: Exploiting dynamic instruction behavior for fast and accurate microarchitecture level reliability assessment
(Association for Computing Machinery (ACM), 2017)
Text en actes de congrés
Accés obertEarly reliability assessment of hardware structures using microarchitecture level simulators can effectively guide major error protection decisions in microprocessor design. Statistical fault injection on microarchitectural ... -
Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm
(2012)
Text en actes de congrés
Accés obert3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant ... -
Modem gain-cell memories in advanced technologies
(Institute of Electrical and Electronics Engineers (IEEE), 2018)
Text en actes de congrés
Accés obertWith the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gain- ... -
MODEST: a model for energy estimation under spatio-temporal variability
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
Text en actes de congrés
Accés restringit per política de l'editorialEstimation of static and dynamic energy of caches is critical for high-performance low-power designs. Commercial CAD tools performing energy estimation statically are not aware of the changing operating and environmental ... -
Nanoelectronic Circuit Design
(Universitat Politècnica de Catalunya, 2016)
Apunts
Accés obert -
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Text en actes de congrés
Accés obertThis special session paper introduces the Horizon Europe NEUROPULS project, which targets the development of secure and energy-efficient RISC-V interfaced neuromorphic accelerators using augmented silicon photonics technology. ...
