3T1D cell has been stated as a valid alternative to be implemented on L1 memory cache to substitute 6T, highly affected by device variability. In this contribution, we have shown that 22nm 3T1D memory cells present significant tolerance to high levels of device parameter fluctuation.
Moreover, we have observed that the variability of the write access transistor has turn into the more detrimental device for
the 3T1D cell performance. Furthermore, resizing and temperature control have been presented as some strategies to mitigate the cell variability.
Best DCIS Paper Award 2012
CitationAmat, E. [et al.]. Mitigation strategies of the variability in 3T1D cell memories scaled beyond 22nm. A: Conference on Design of Circuits and Integrated Systems. "Proceedings of DCIS 2012 : XXVII Design of Circuits and Integrated Systems Conference". Avignon: 2012, p. 1-5.
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