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Ara es mostren els items 74-93 de 175

    • Fast time-to-market with via-configurable transistor array regular fabric: A delay-locked loop design case study 

      González Colás, Antonio María; Pons Solé, Marc; Barajas Ojeda, Enrique; Mateo Peña, Diego; López González, Juan Miguel; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier (IEEE Computer Society Publications, 2011)
      Comunicació de congrés
      Accés restringit per política de l'editorial
      Time-to-market is a critical issue for nowadays integrated circuits manufacturers. In this paper the Via-Configurable Transistor Array regular layout fabric (VCTA), which aims to minimize the time-to-market and its associated ...

    • Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy 

      Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio (2010)
      Text en actes de congrés
      Accés obert
      One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS ...

    • Fault-tolerant nanoscale architecture based on linear threshold gates with redundancy 

      Aymerich Capdevila, Nivard; Rubio Sola, Jose Antonio (2012-07)
      Article
      Accés restringit per política de l'editorial
      One of the main objectives of the data computing and memory industry is to keep and ever accelerate the increase of component density reached in nowadays integrated circuits in future technologies based on ultimate CMOS ...

    • Final Exam. Part 2 

      Rubio Sola, Jose Antonio (Universitat Politècnica de Catalunya, 2021-06-02)
      Examen
      Accés restringit a la comunitat UPC

    • FinFET and III-V/Ge technology impact on 3T1D cell behavior 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; Almudever, Carmen G.; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013)
      Comunicació de congrés
      Accés obert
      In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability ...

    • FOCSI: A new layout regularity metric 

      Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María (2009-06-09)
      Report de recerca
      Accés obert
      Digital CMOS Integrated Circuits (ICs) suffer from serious layout features printability issues associated to the lithography manufacturing process. Regular layout designs are emerging as alternative solutions to reduce ...

    • Four different approaches for the measurement of IC surface temperature: Application to thermal testing 

      Saulnier, J.B; Altet Sanahujes, Josep; Dilhaire, Stefan; Volz, S.; Rampnoux, J.M.; Rubio Sola, Jose Antonio; Grauby, S.; Patino, L.; Claeys, W. (2002-09)
      Article
      Accés restringit per política de l'editorial
      Silicon die surface temperature can be used to monitor the health state of digital and analogue integrated circuits (IC). In the present paper, four different sensing techniques: scanning thermal microscope, laser ...

    • Hardware design of memristor-based oscillators for emulation of neurological diseases 

      Chatzipaschalis, Ioannis; Tsipas, Evangelos; Tsakalos, Karolos-Alexandros; Rubio Sola, Jose Antonio; Sirakoulis, Georgios Ch. (Institute of Electrical and Electronics Engineers (IEEE), 2023)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      One of the most prominent examples of a complex system in nature is the nervous system, which exhibits oscillation phenomena across its structures, from single neurons to sophisticated neural networks. Memristors have been ...

    • Heterogeneous memristive crossbar for in-memory computing 

      Papandroulidakis, Georgios; Vourkas, Ioanis; Sirakoulis, Georgios Ch.; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Text en actes de congrés
      Accés obert
      It's been quite a while since scientists are seeking for the ancestor of von Neumann computing architecture. Among the most promising candidates, memristor demonstrates advantageous characteristics, which open new pathways ...

    • High level spectral-based análisis of power concumption in DSP's systems 

      Calomarde Palomino, Antonio; Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2006)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      In this paper, an efficient technique to evaluate temporal correlation and transition activity at high level in DSP systems is presented. The method is based on the spectral distribution of signals and has the advantage ...

    • Impact of adaptive proactive reconfiguration technique on Vmin and lifetime of SRAM caches 

      Pouyan, Peyman; Amat Bertran, Esteve; Barajas Ojeda, Enrique; Rubio Sola, Jose Antonio (2014)
      Text en actes de congrés
      Accés obert
      This work presents a test and measurement technique to monitor aging and process variation status of SRAM cells as an aging-aware design technique. We have then verified our technique with an implemented chip. The obtained ...

    • Impact of finfet and III-V/Ge technology on logic and memory cell behavior 

      Amat Bertran, Esteve; Calomarde Palomino, Antonio; García Almudéver, Carmen; Aymerich Capdevila, Nivard; Canal Corretger, Ramon; Rubio Sola, Jose Antonio (2013-11-20)
      Article
      Accés restringit per política de l'editorial
      In this work, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFET and III-V MOSFETs), and subjected to different reliability scenarios ...

    • Impact of positive bias temperature instability (PBTI) 

      Aymerich Capdevila, Nivard; Ganapathy, Shrikanth; Rubio Sola, Jose Antonio; Canal Corretger, Ramon; González Colás, Antonio María (2011)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      Memory circuits are playing a key role in complex multicore systems with both data and instructions storage and mailbox communication functions. There is a general concern that conventional SRAM cell based on the 6T structure ...

    • Implementation of a 5x5 trits multiplier in a quasi-adiabatic ternary CMOS logic 

      Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 1997)
      Text en actes de congrés
      Accés obert
      Adiabatic switching is one technique to design low power digital IC. In order to diminish its expensive silicon area requirements an adiabatic ternary logic is proposed. A 5×5 trits (ternary signals) multiplier has been ...

    • Influence of punch trough stop layer and well depths on the robustness of bulk FinFETs to heavy ions impact 

      Calomarde Palomino, Antonio; Manich Bou, Salvador; Rubio Sola, Jose Antonio; Gamiz, Francisco (Institute of Electrical and Electronics Engineers (IEEE), 2022-05-02)
      Article
      Accés obert
      This study analyzes the effects of the punch-through stop (PTS) layer and well depth in a bulk FinFET SRAM cell on the fraction of charge generated by an ion impact that is collected by the FinFET channel. More than 1700 ...

    • INFORMER: an integrated framework for early-stage memory robustness analysis 

      Ganapathy, Shrikanth; Canal Corretger, Ramon; Alexandrescu, Dan; Costenaro, Eric; González Colás, Antonio María; Rubio Sola, Jose Antonio (European Interactive Digital Advertising Alliance (EDAA), 2014)
      Text en actes de congrés
      Accés restringit per política de l'editorial
      With the growing importance of parametric (process and environmental) variations in advanced technologies, it has become a serious challenge to design reliable, fast and low-power embedded memories. Adopting a variation-aware ...

    • Insights to memristive memory cell from a reliability perspective 

      Pouyan, Peyman; Amat Bertran, Esteve; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2015)
      Text en actes de congrés
      Accés obert
      The scaling roadmap of devices under a more than Moore scenario is resulting in the emergence of new types of devices. Among them, memristors seem to be promising candidates to be suitable for various areas of application ...

    • Introduction to VHDL I 

      Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
      Audiovisual
      Accés obert

    • Introduction to VHDL II 

      Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
      Audiovisual
      Accés obert

    • Introduction to VHDL III 

      Altet Sanahujes, Josep; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2020-09-22)
      Audiovisual
      Accés obert