Now showing items 1-5 of 5

  • Control-flow speculation through value prediction 

    González, José; González Colás, Antonio María (2001-12)
    Article
    Restricted access - publisher's policy
    In this paper, we introduce a new branch predictor that predicts the outcome of branches by predicting the value of their inputs and performing an early computation of their results according to the predicted values. The ...
  • Enlarging instruction streams 

    Santana Jaria, Oliverio J.; Ramírez Bellido, Alejandro; Valero Cortés, Mateo (2007-10)
    Article
    Open Access
    The stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially ...
  • Instruction fetch architectures and code layout optimizations 

    Ramírez Bellido, Alejandro; Larriba Pey, Josep; Valero Cortés, Mateo (2001-11)
    Article
    Open Access
    The design of higher performance processors has been following two major trends: increasing the pipeline depth to allow faster clock rates, and widening the pipeline to allow parallel execution of more instructions. Designing ...
  • Software trace cache 

    Ramírez Bellido, Alejandro; Larriba Pey, Josep; Valero Cortés, Mateo (2005-01)
    Article
    Open Access
    We explore the use of compiler optimizations, which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying hardware resources regardless of the specific details ...
  • Thread partitioning and value prediction for exploiting speculative thread-level parallelism 

    Marcuello, Pedro; González Colás, Antonio María; Tubella Murgadas, Jordi (2004-02)
    Article
    Open Access
    Speculative thread-level parallelism has been recently proposed as a source of parallelism to improve the performance in applications where parallel threads are hard to find. However, the efficiency of this execution model ...