Exploració per autor "Quiñones, Eduardo"
Ara es mostren els items 27-46 de 61
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Leveraging register windows to reduce physical registers to the bare minimum
(2010-12)
Article
Accés obertRegister window is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register requirements ... -
Measurement-based probabilistic timing analysis for multi-path programs
(2012)
Text en actes de congrés
Accés restringit per política de l'editorialThe rigorous application of static timing analysis requires a large and costly amount of detail knowledge on the hardware and software components of the system. Probabilistic Timing Analysis has potential for reducing the ... -
Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialProbabilistic Timing Analysis (PTA) in general and its measurement-based variant called MBPTA in particular can mitigate some of the problems that impair current worst-case execution time (WCET) analysis techniques. MBPTA ... -
Measurement-based timing analysis of the AURIX caches
(Schloss Dagstuhl - Leibniz-Zentrum für Informatik, 2016)
Text en actes de congrés
Accés obertCache memories are one of the hardware resources with higher potential to reduce worst-case execution time (WCET) costs for software programs with tight real-time constraints. Yet, the complexity of cache analysis has ... -
Modeling high-performance wormhole NoCs for critical real-time embedded systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertManycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's ... -
Modelling the confidence of timing analysis for time randomised caches
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertTiming is a key non-functional property in embedded real-Time systems (ERTS). ERTS increasingly require higher levels of performance that can only be sensibly provided by deploying high-performance hardware, which however ... -
Multi-level unified caches for probabilistically time analysable real-time systems
(IEEEXPLORE, 2013)
Text en actes de congrés
Accés restringit per política de l'editorialCaches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, ... -
On the convergence of mainstream and mission-critical markets
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialThe computing market has been dominated during the last two decades by the well-known convergence of the highperformance computing market and the mobile market. In this paper we witness a new type of convergence between ... -
OpenMP static TDG runtime implementation and its usage in heterogeneous computing
(Barcelona Supercomputing Center, 2020-05)
Text en actes de congrés
Accés obertOpenMP being the standard to use in shared memory parallel programming, it offers the possibility to parallelize sequential program with accelerators by using target directive. However, CUDA Graph as a new, efficient ... -
Parcus: Energy-Aware and Robust Parallelization of AUTOSAR Legacy Applications
(Institute of Electrical and Electronics Engineers (IEEE), 2017-06-08)
Comunicació de congrés
Accés obertEmbedded multicore processors are an attractive alternative to sophisticated single-core processors for the use in automobile electronic control units (ECUs), due to their expected higher performance and energy efficiency. ... -
Probabilistic timing analysis on conventional cache designs
(2013)
Text en actes de congrés
Accés restringit per política de l'editorialProbabilistic timing analysis (PTA), a promising alternative to traditional worst-case execution time (WCET) analyses, enables pairing time bounds (named probabilistic WCET or pWCET) with an exceedance probability (e.g., ... -
Probabilistic timing analysis on time-randomized platforms for the space domain
(Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
Comunicació de congrés
Accés obertTiming Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that ... -
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis
(IEEE, 2016-08-31)
Comunicació de congrés
Accés obertThe use of increasingly complex hardware and software platforms in response to the ever rising performance demands of modern real-time systems complicates the verification and validation of their timing behaviour, which ... -
pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertThe use of networks-on-chip (NoC) in real-time safety-critical multicore systems challenges deriving tight worst-case execution time (WCET) estimates. This is due to the complexities in tightly upper-bounding the contention ... -
Real-time Issues in the Ada Parallel Model with OpenMP
(Association for Computing Machinery, 2021)
Article
Accés obertThe current proposal for the next revision of the Ada language considers the possibility to map the language parallel features to an underlying OpenMP runtime. As previously presented, and discussed in previous workshops, ... -
Response-time analysis of DAG tasks supporting heterogeneous computing
(Association for Computing Machinery (ACM), 2018-06-24)
Comunicació de congrés
Accés obert -
Response-time analysis of DAG tasks under fixed priority scheduling with limited preemptions
(Institute of Electrical and Electronics Engineers (IEEE), 2016-03-14)
Text en actes de congrés
Accés obertLimited preemptive (LP) scheduling has been demonstrated to effectively improve the schedulability of fully preemptive (FP) and fully non-preemptive (FNP) paradigms. On one side, LP reduces the preemption related overheads ... -
RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores
(Association for Computing Machinery (ACM), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialAutomotive applications increasingly rely on AUTOSAR for their design and execution. AUTOSAR applications comprise functions, called runnables, that are grouped into AUTOSAR tasks. Tasks are the unit of scheduling (UoS) ... -
RVC: A mechanism for time-analyzable real-time processors with faulty caches
(2011)
Text en actes de congrés
Accés restringit per política de l'editorialGeometry scaling due to technology evolution as well as Vcc scaling lead to failures in large SRAM arrays such as caches. Faulty bits can be tolerated from the average performance perspective, but make critical realtime ... -
Seeking time-composable partitions of tasks for COTS multicore processors
(Institute of Electrical and Electronics Engineers (IEEE), 2015)
Comunicació de congrés
Accés obertThe timing verification of real-time single core systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling attributes ...
