Exploració per autor "González Colás, Antonio María"
Ara es mostren els items 159-178 de 237
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P-slice based efficient speculative multithreading
(IEEE Computer Society Publications, 2009-12-16)
Text en actes de congrés
Accés obertMicroprocessor industry has recently shifted towards multi-core to take advantage of the ever increasing number of transistors provided by the new technologies. Unfortunately, the multi-core approach does not allow single ... -
PARSAR: A SAR processor implemented in a cluster of workstations
(ESA Publications Division, 1997)
Text en actes de congrés
Accés obertA parallel SAR processor is presented in this paper. The target configuration is a cluster of UNIX workstations, available in most user sites. This fact allows to obtain an increased computing performance without the need ... -
PARSAR: Parallelisation of a chirp scaling algorithm SAR processor
(Ch. Lengauer, M. Grielb, S. Gorlatch. BERLIN, NEW YORK, Springer-Verlag Cop.1997, 1997)
Text en actes de congrés
Accés obertA parallel SAR processor is presented in this paper. The target configuration is a cluster of UNIX workstations, available in most user sites. This fact allows to obtain an increased computing performance without the need ... -
Parsar: parallelisation of a chirp scaling algorithm sar processor
(1997-08)
Article
Accés restringit per política de l'editorialA parallel SAR processor is presented in this paper. The target configuration is a cluster of UNIX workstations, available in most user sites. This fact allows to obtain an increased computing performance without the need ... -
Penelope: The NBTI-aware processor
(IEEE Computer Society, 2007)
Text en actes de congrés
Accés obertTransistors consist of lower number of atoms with every technology generation. Such atoms may be displaced due to the stress caused by high temperature, frequency and current, leading to failures. NBTI (negative bias ... -
Performance analysis and optimization of automatic speech recognition
(2018-10-01)
Article
Accés obertFast and accurate Automatic Speech Recognition (ASR) is emerging as a key application for mobile devices. Delivering ASR on such devices is challenging due to the compute-intensive nature of the problem and the power ... -
Performance analysis of non-uniform cache architecture policies for chip-multiprocessors using the Parsec v2.0 Benchmark Suite
(2009-09)
Text en actes de congrés
Accés restringit per política de l'editorialNon-Uniform Cache Architectures (NUCA)have been proposed as a solution to overcome wire delays that will dominate on-chip latencies in Chip Multiprocessor designs in the near future. This novel means of organization divides ... -
Power efficient data cache designs
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertWe investigate some power efficient data cache designs that try to significantly reduce the cache energy consumption, both static and dynamic, with a minimal impact in performance. The basic idea is to combine different ... -
Power- and complexity-aware issue queue designs
(2003-09)
Article
Accés obertThe improved performance of current microprocessors brings with it increasingly complex and power-dissipating issue logic. Recent proposals introduce a range of mechanisms for tackling this problem. -
Power-aware control speculation through selective throttling
(Institute of Electrical and Electronics Engineers (IEEE), 2003)
Text en actes de congrés
Accés obertWith the constant advances in technology that lead to the increasing of the transistor count and processor frequency, power dissipation is becoming one of the major issues in high-performance processors. These processors ... -
Power/performance/thermal design-space exploration for multicore architectures
(2008-05)
Article
Accés obertMulticore architectures have been ruling the recent microprocessor design trend. This is due to different reasons: better performance, thread-level parallelism bounds in modern applications, ILP diminishing returns, better ... -
QeiHaN: An energy-efficient DNN accelerator that leverages log quantization in NDP architectures
(Institute of Electrical and Electronics Engineers (IEEE), 2023)
Comunicació de congrés
Accés obertThe constant growth of DNNs makes them challenging to implement and run efficiently on traditional computecentric architectures. Some works have attempted to enhance accelerators by adding more compute units and on-chip ... -
Quantitative characterization of the software layer of a HW/SW co-designed processor
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertHW/SW co-designed processors currently have a renewed interest due to their capability to boost performance without running into the power and complexity walls. By employing a software layer that performs dynamic binary ... -
Randomized cache placement for eliminating conflicts
(1999-02)
Article
Accés obertApplications with regular patterns of memory access can experience high levels of cache conflict misses. In shared-memory multiprocessors conflict misses can be increased significantly by the data transpositions required ... -
Reducing branch delay to zero in pipelined processors
(1993-03)
Article
Accés obertA mechanism to reduce the cost of branches in pipelined processors is described and evaluated. It is based on the use of multiple prefetch, early computation of the target address, delayed branch, and parallel execution ... -
Reducing DUE-FIT of caches by exploiting acoustic wave detectors for error recovery
(IEEE Computer Society Publications, 2013)
Text en actes de congrés
Accés restringit per política de l'editorialCosmic radiation induced soft errors have emerged as a key challenge in computer system design. The exponential increase in the transistor count will drive the per chip fault rate sky high. New techniques for detecting ... -
Reducing soft errors through operand width aware policies
(2009-09)
Article
Accés obertSoft errors are an important challenge in contemporary microprocessors. Particle hits on the components of a processor are expected to create an increasing number of transient errors with each new microprocessor generation. ... -
Reducing wire delay penalty through value prediction
(Institute of Electrical and Electronics Engineers (IEEE), 2000)
Text en actes de congrés
Accés obertIn this paper we show that value prediction can be used to avoid the penalty of long wire delays by predicting the data that is communicated through these long wires and validating the prediction locally where the value ... -
Refueling: Preventing wire degradation due to electromigration
(2008-12)
Article
Accés obertElectromigration is a major source of wire and via failure. Refueling undoes EM for bidirectional wires and power/ground grids-some of a chip's most vulnerable wires. Refueling exploits EM's self-healing effect by balancing ... -
Reliability: fallacy or reality?
(2007-11)
Article
Accés obertAs chip architects and manufacturers plumb ever-smaller process technologies, new species of faults are compromising device reliability, following an introduction by the authors debate whether reliability is a legitimate ...
