Exploració per tema "CMOS logic circuits"

Ara es mostren els items 1-7 de 7

    • An approach to dynamic power consumption current testing of CMOS ICs 

      Segura, J A; ROCA, M; Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 1995)
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      I/sub DDQ/ testing is a powerful strategy for detecting defects that do not alter the logic behavior of CMOS ICs. Such a technique is very effective especially in the detection of bridging defects although some opens can ...

    • Asynchronous multipliers with variable-delay counters 

      Cornetta, Gianluca; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 2001)
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      Although multiplication is an intensely studied arithmetic operation and many fast algorithms and implementations are available, it still represents one of the major bottlenecks of many digital systems that require intensive ...

    • Asynchronous pulse logic cell for threshold logic and Boolean networks 

      Lambie, J; Moll Echeto, Francisco de Borja; González Jiménez, José Luis; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 2005)
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      Accés restringit per política de l'editorial
      In this article, a fully digital CMOS circuit for asynchronous pulse cells is presented. The proposed circuit has a high noise tolerance and no static power consumption. Furthermore it has a high functional programmability. ...

    • Design and implementation of a 5/spl times/5 trits multiplier in a quasi-adiabatic ternary CMOS logic 

      Mateo Peña, Diego; Rubio Sola, Jose Antonio (1998-07)
      Article
      Accés obert
      Adiabatic switching is a technique to design low-power digital IC's. Fully adiabatic logics have expensive silicon area requirements. To solve this drawback, a quasi-adiabatic ternary logic is proposed. Its basis is ...

    • Implementation of a 5x5 trits multiplier in a quasi-adiabatic ternary CMOS logic 

      Mateo Peña, Diego; Rubio Sola, Jose Antonio (Institute of Electrical and Electronics Engineers (IEEE), 1997)
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      Accés obert
      Adiabatic switching is one technique to design low power digital IC. In order to diminish its expensive silicon area requirements an adiabatic ternary logic is proposed. A 5×5 trits (ternary signals) multiplier has been ...

    • Novel redundant logic design for noisy low voltage scenarios 

      García Leyva, Lancelot; Calomarde Palomino, Antonio; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio (2013)
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      The concept worked in this paper named Turtle Logic (TL) is a probabilistic logic method based on port redundancy and complementary data, oriented to emerging CMOS technologies and beyond, where the thermal noise could be ...

    • Optimizing CMOS circuits for low power using transistor reordering 

      Musoll Cinca, Enric; Cortadella, Jordi (Institute of Electrical and Electronics Engineers (IEEE), 1996)
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      This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power internal nodes of the gate. ...