Exploració per autor "Slijepcevic, Mladen"
Ara es mostren els items 1-10 de 10
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Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis
(IEEE, 2017-09-28)
Comunicació de congrés
Accés obertWormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical ... -
Design and implementation of a fair credit-based bandwidth sharing scheme for buses
(Institute of Electrical and Electronics Engineers (IEEE), 2017-05-15)
Comunicació de congrés
Accés obertFair arbitration in the access to hardware shared resources is fundamental to obtain low worst-case execution time (WCET) estimates in the context of critical real-time systems, for which performance guarantees are essential. ... -
DTM: degraded test mode for fault-aware probabilistic timing analysis
(Institute of Electrical and Electronics Engineers (IEEE), 2013)
Text en actes de congrés
Accés restringit per política de l'editorialExisting timing analysis techniques to derive Worst-Case Execution Time (WCET) estimates assume that hardware in the target platform (e.g., the CPU) is fault-free. Given the performance requirements increase in current ... -
Probabilistically time-analyzable complex processor designs
(Universitat Politècnica de Catalunya, 2017-11-13)
Tesi
Accés obertIndustry developing Critical Real-Time Embedded Systems (CRTES), such as Aerospace, Space, Automotive and Railways, faces relentless demands for increased guaranteed processor performance to support new advanced functionalities ... -
Probabilistically time-analyzable complex processors in hard real- time systems
(Barcelona Supercomputing Center, 2015-05-05)
Text en actes de congrés
Accés obertCritical Real-Time Embedded Systems (CRTES) feature performance-demanding functionality. High-performance hardware and complex software can provide such functionality, but the use of aggressive technology challenges ... -
PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis
(IEEE, 2016-08-31)
Comunicació de congrés
Accés obertThe use of increasingly complex hardware and software platforms in response to the ever rising performance demands of modern real-time systems complicates the verification and validation of their timing behaviour, which ... -
pTNoC: Probabilistically time-analyzable tree-based NoC for mixed-criticality systems
(Institute of Electrical and Electronics Engineers (IEEE), 2016)
Text en actes de congrés
Accés obertThe use of networks-on-chip (NoC) in real-time safety-critical multicore systems challenges deriving tight worst-case execution time (WCET) estimates. This is due to the complexities in tightly upper-bounding the contention ... -
Time-analysable non-partitioned shared caches for real-time multicore systems
(Association for Computing Machinery (ACM), 2014)
Text en actes de congrés
Accés restringit per política de l'editorialShared caches in multicores challenge Worst-Case Execution Time (WCET) estimation due to inter-task interferences. Hard-ware and software cache partitioning address this issue although they complicate data sharing among ... -
Time-Randomized Wormhole NoCs for Critical Applications
(Association for Computing Machinery (ACM), 2019-02)
Article
Accés obertWormhole-based NoCs (wNoCs) are widely accepted in high-performance domains as the most appropriate solution to interconnect an increasing number of cores in the chip. However, wNoCs suitability in the context of critical ... -
Timing verification of fault-tolerant chips for safety-critical applications in harsh environments
(2014-11-01)
Article
Accés restringit per política de l'editorialCritical real-time embedded systems feature complex safety-related, performance-demanding functionality. High-performance hardware and software can provide such functionality, but the use of aggressive technologies and ...
