Timing verification of fault-tolerant chips for safety-critical applications in harsh environments
Rights accessRestricted access - publisher's policy
Critical real-time embedded systems feature complex safety-related, performance-demanding functionality. High-performance hardware and software can provide such functionality, but the use of aggressive technologies and architectures challenges time predictability and reliability. The authors propose a new approach to obtain trustworthy worst-case execution time estimates for safety-critical applications running on high-performance faulty hardware by using both timing-analysis techniques and minor hardware modifications.
CitationSlijepcevic, M. [et al.]. Timing verification of fault-tolerant chips for safety-critical applications in harsh environments. "IEEE micro", 01 Novembre 2014, vol. 34, núm. 6, p. 7-18.
|Timing verifica ... in harsh environments.pdf||Timing verification of fault tolerant chips for safety critical applications in harsh environments||629.1Kb||Restricted access|