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Reactive clocks with variability-tracking jitter
dc.contributor.author | Cortadella, Jordi |
dc.contributor.author | Lavagno, Luciano |
dc.contributor.author | López Muñoz, Pedro |
dc.contributor.author | Lupon Navazo, Marc |
dc.contributor.author | Moreno Vega, Alberto |
dc.contributor.author | Roca Pérez, Antoni |
dc.contributor.author | Sapatnekar, Sachin S. |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
dc.date.accessioned | 2016-04-05T11:41:46Z |
dc.date.available | 2016-04-05T11:41:46Z |
dc.date.issued | 2015 |
dc.identifier.citation | Cortadella, J., Lavagno, L., López, P., Lupon, M., Moreno, A., Roca, A., Sapatnekar, S. Reactive clocks with variability-tracking jitter. A: IEEE International Conference on Computer Design. "Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD): 18-21 October 2015, New York City, USA". New York: Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 511-518. |
dc.identifier.isbn | 978-1-4673-7165-0 |
dc.identifier.uri | http://hdl.handle.net/2117/85192 |
dc.description | © 2015 IEEE.Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. |
dc.description.abstract | The growing variability in nanoelectronic devices, due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging), requires increasing design guardbands, forcing circuits to work with conservative clock frequencies. Various schemes for clock generation based on ring oscillators and adaptive clocks have been proposed with the goal to mitigate the power and performance losses attributable to variability. However, there has been no systematic analysis to quantify the benefits of such schemes and no sign-off method has been proposed for timing correctness. This paper presents and analyzes a Reactive Clocking scheme with Variability-Tracking Jitter (RClk) that uses variability as an opportunity to reduce power by continuously adjusting the clock frequency to the varying environmental conditions, and thus, reduces guardband margins significantly. Power can be reduced between 20% and 40% at iso-performance and performance can be boosted by similar amounts at iso-power. Additionally, energy savings can be translated to substantial advantages in terms of reliability and thermal management. More importantly, the technology can be adopted with minimal modifications to conventional EDA flows. |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica |
dc.subject.lcsh | Nanoelectronics |
dc.subject.lcsh | Integrated circuits -- Reliability |
dc.subject.other | Clocks |
dc.subject.other | Oscillators |
dc.subject.other | Performance evaluation |
dc.subject.other | Power aware computing |
dc.subject.other | Thermal management (packaging) |
dc.subject.other | Timing jitter |
dc.title | Reactive clocks with variability-tracking jitter |
dc.type | Conference report |
dc.subject.lemac | Nanoelectrònica |
dc.subject.lemac | Circuits integrats -- Fiabilitat |
dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
dc.identifier.doi | 10.1109/ICCD.2015.7357159 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7357159 |
dc.rights.access | Open Access |
local.identifier.drac | 17510196 |
dc.description.version | Postprint (author's final draft) |
local.citation.author | Cortadella, J.; Lavagno, L.; López, P.; Lupon, M.; Moreno, A.; Roca, A.; Sapatnekar, S. |
local.citation.contributor | IEEE International Conference on Computer Design |
local.citation.pubplace | New York |
local.citation.publicationName | Proceedings of the 33rd IEEE International Conference on Computer Design (ICCD): 18-21 October 2015, New York City, USA |
local.citation.startingPage | 511 |
local.citation.endingPage | 518 |