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Adaptive clock with useful jitter
(2015-05-19)
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Report de recerca.
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The growing variability in nanoelectronic devices due to uncertainties from the manufacturing process and environmental conditions (power supply, temperature, aging) requires increasing design guardbands, forcing circuits ...
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
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Presents a new technique for the decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available in ...
Automatic generation of synchronous test patterns for asynchronous circuits
(Institute of Electrical and Electronics Engineers (IEEE), 1997)
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This paper presents a novel approach for automatic test pattern generation of asynchronous circuits. The techniques used for this purpose assume that the circuit can only be exercised by applying synchronous test vectors, ...
Decomposition and technology mapping of speed-independent circuits using Boolean relations
(1999-09)
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Article.
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This paper presents a new technique for decomposition and technology mapping of speed-independent circuits. An initial circuit implementation is obtained in the form of a netlist of complex gates, which may not be available ...
Complete state encoding based on the theory of regions
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
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Synthesis of asynchronous circuits from Signal Transition Graphs (STGs) and/or State Graphs (SGs) involves solving state coding problems. A well-known example of such problems is that of Complete State Coding (CSC), which ...
Elastic systems
(Institute of Electrical and Electronics Engineers (IEEE), 2010)
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Elastic systems provide tolerance to the variations in computation and communication delays. The incorporation of elasticity opens new opportunities for optimization using new correct-by-construction transformations that ...
Individual flip-flops with gated clocks for low power datapaths
(Institute of Electrical and Electronics Engineers (IEEE), 1997-06)
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Energy consumption has become one of the important factors in digital systems, because of the requirement to dissipate this energy in high-density circuits and to extend the battery life in portable systems such as devices ...
Structural methods for the synthesis of speed-independent circuits
(1998-11)
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Article.
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Asynchronous circuits can be modeled as concurrent systems in which events are interpreted as signal transitions. The synthesis of concurrent systems implies the analysis of a vast state space that often requires computationally ...
High-level synthesis techniques for reducing the activity of functional units
(Association for Computing Machinery (ACM), 1995)
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Decisions taken at the earliest steps of the design process may have a significant impact on the characteristics of the final implementation. This paper illustrates how power consumption issues can be tackled during ...
Optimizing CMOS circuits for low power using transistor reordering
(Institute of Electrical and Electronics Engineers (IEEE), 1996)
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This paper addresses the optimization of a circuit for low power using transistor reordering. The optimization algorithm relies on a stochastic model of a static CMOS gate that includes the power internal nodes of the gate. ...