Ara es mostren els items 1-16 de 16

  • A unifying framework for the definition of syntactic measures over conceptual schema diagrams (extended version) 

    Costal Costa, Dolors; Franch Gutiérrez, Javier (2011-07-20)
    Report de recerca
    Accés obert
    There are many approaches that propose the use of measures for assessing the quality of conceptual schemas. Many of these measures focus purely on the syntactic aspects of the conceptual schema diagrams, e.g. their size, ...
  • Banda sonora discriminatòria pel control de la velocitat del trànsit en carreteres 

    Ustrell i Mussons, Raül (Universitat Politècnica de Catalunya, 2008-03)
    Projecte/Treball Final de Carrera
    Accés obert
    Aquest projecte pretén desenvolupar un mecanisme capaç d’aportar una millora en la funció que fan les bandes sonores que es troben instal·lades actualment en les carreteres i nuclis urbans, però sense la sèrie d’inconvenients ...
  • Computer-based system for control and circuit analysis 

    Bertran Albertí, Eduardo; Guimerà, A. (1985)
    Text en actes de congrés
    Accés obert
  • Desenvolupament d'un editor de casos de prova estructurals i executables sobre un esquema conceptual del sistema 

    Dueñas Juez, Patricio (Universitat Politècnica de Catalunya, 2016-06-29)
    Projecte/Treball Final de Carrera
    Accés obert
    Realitzat a/amb: Sogeti
    Desenvolupament d'un editor de casos de prova estructurats i executables sobre un esquema conceptual del sistema: - Memòria del Projecte - Codi font del prototip funcional de la prova de concepte
  • Design of highly synchronizable and robust networks 

    Estrada Roger, Ernesto; Gago Álvarez, Silvia; Caporossi, Gilles (2010-11)
    Article
    Accés restringit per política de l'editorial
    In this paper, the design of highly synchronizable, sparse and robust dynamical networks is addressed. Better synchronizability means faster synchronization of the oscillators, sparsity means a low ratio of links per ...
  • Dynamic selective devectorization for efficient power gatting of SIMD units in a HW/SW co-designed enviromment 

    Kumar, Rakesh; Martínez, Alejandro; González Colás, Antonio María (IEEE Computer Society Publications, 2013)
    Text en actes de congrés
    Accés obert
    Leakage power is a growing concern in current and future microprocessors. Functional units of microprocessors are responsible for a major fraction of this power. Therefore, reducing functional unit leakage has received ...
  • Expert system design for sewage treatment plant 

    Bouza Fernández, Javier; Gonzalez Filgueira, Gerardo; Heras Jiménez, Salvador Augusto de las; Vazquez Gonzalez, David (InTech, 2012-04-20)
    Capítol de llibre
    Accés obert
  • FaulTM: Error detection and recovery using hardware transactional memory 

    Yalcin, Gulay; Unsal, Osman Sabri; Cristal Kestelman, Adrián (2013)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Reliability is an essential concern for processor designers due to increasing transient and permanent fault rates. Executing instruction streams redundantly in chip multi processors (CMP) provides high reliability since ...
  • Hybrid turbo FEC/ARQ systems and distributed space-time coding for cooperative transmission 

    Agustín de Dios, Adrián; Vidal Manzano, José; Muñoz Medina, Olga (2005-08-24)
    Article
    Accés obert
    Cooperative transmission can be seen as a "virtual" MIMO system, where the multiple transmit antennas are in fact implemented distributed by the antennas both at the source and the relay terminal. Depending on the system ...
  • Impact of the memory hierarchy on shared memory architectures in multicore programming models 

    Badia Sala, Rosa Maria; Pérez Cáncer, Josep Maria; Ayguadé Parra, Eduard; Labarta Mancho, Jesús José (IEEE Computer Society Publications, 2009)
    Comunicació de congrés
    Accés obert
    Many and multicore architectures put a big pressure in parallel programming but gives a unique opportunity to propose new programming models that automatically exploit the parallelism of these architectures. OpenMP is a ...
  • ITCA: inter-task conflict-aware CPU accounting for CMPs 

    Luque, Carlos; Moreto Planas, Miquel; Cazorla Almeida, Francisco Javier; Gioiosa, Roberto; Buyuktosunoglu, Alper; Valero Cortés, Mateo (IEEE Computer Society Publications, 2009)
    Text en actes de congrés
    Accés restringit per política de l'editorial
  • Multi-level unified caches for probabilistically time analysable real-time systems 

    Kosmidis, Leonidas; Abella Ferrer, Jaume; Quiñones Moreno, Eduardo; Cazorla Almeida, Francisco Javier (IEEEXPLORE, 2013)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    Caches are key resources in high-end processor architectures to increase performance. In fact, most high-performance processors come equipped with a multi-level cache hierarchy. In terms of guaranteed performance, however, ...
  • OS paradigms adaptation to fit new architectures 

    Joglar, Xavi; Planas Carbonell, Judit; Gil, Marisa (2008)
    Comunicació de congrés
    Accés obert
    Future architectures and computer systems will be heterogeneous multi-core models, which will improve their performance, resource utilization and energy consumption. Differences between cores mean different binary formats ...
  • Proyecto de instalaciones de protección contra incendios en un gran centro logístico con oficinas 

    Reluy Domínguez, Arturo (Universitat Politècnica de Catalunya, 2011)
    Projecte/Treball Final de Carrera
    Accés obert
    El presente trabajo de fin de carrera tiene como objetivo el estudio de la normativa en materia de sistemas de protección contra incendio, con el fin de realizar el diseño de una instalación ficticia. El punto principal ...
  • Simulació d'un projecte realitzat per una consultora informàtica 

    Mas Capdevila, Salvador (Universitat Politècnica de Catalunya, 2007-06-26)
    Projecte/Treball Final de Carrera
    Accés obert
    En aquest projecte s’ha intentat simular la forma de treball d’una consultora informàtica desde el moment que realitza un pressupost fins a la entrega del programa acabat i posta en marxa del mateix. S’ha creat una ...
  • Using randomized caches in probabilistic real-time systems 

    Quiñones, Eduardo; Berger, Emery D.; Bernat, Guillem; Cazorla Almeida, Francisco Javier (2009)
    Text en actes de congrés
    Accés restringit per política de l'editorial
    While hardware caches are generally effective at improving application performance, they greatly complicate performance prediction. Slight changes in memory layout or data access patterns can lead to large and ...