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Specification mining for asynchronous controllers
| dc.contributor.author | San Pedro Martín, Javier de |
| dc.contributor.author | Bourgeat, Thomas |
| dc.contributor.author | Cortadella, Jordi |
| dc.contributor.other | Universitat Politècnica de Catalunya. Departament de Ciències de la Computació |
| dc.date.accessioned | 2017-01-24T13:19:10Z |
| dc.date.available | 2017-01-24T13:19:10Z |
| dc.date.issued | 2016 |
| dc.identifier.citation | San Pedro, J. de, Bourgeat, T., Cortadella, J. Specification mining for asynchronous controllers. A: IEEE International Symposium on Asynchronous Circuits and Systems. "22nd IEEE International Symposium on Asynchronous Circuits and Systems: 8-11 May 2016 Porto Alegre, Brazil: proceedings". Porto Alegre: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 107-114. |
| dc.identifier.isbn | 978-1-4673-9007-1 |
| dc.identifier.uri | http://hdl.handle.net/2117/99949 |
| dc.description.abstract | The paper presents a first effort at exploring a novel area in the domain of asynchronous controllers: specification mining. Rather than synthesizing circuits from specifications, we aim at doing reverse engineering, i.e., discovering safe specifications from the circuits that preserve a set of pre-defined behavioral properties (e.g., hazard freeness). The specifications are discovered without any previous knowledge of the behavior of the circuit environment. This area may open new opportunities for re-synthesis and verification of asynchronous controllers. The effectiveness of the proposed approach is demonstrated by mining concurrent specifications (Signal Transition Graphs) from multiple implementations of 4-phase handshake controllers and some controllers with choice. |
| dc.format.extent | 8 p. |
| dc.language.iso | eng |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
| dc.subject.lcsh | Logic design |
| dc.subject.lcsh | Asynchronous circuits |
| dc.subject.other | Controllers |
| dc.subject.other | Reverse engineering |
| dc.subject.other | Specification mining |
| dc.subject.other | Asynchronous controllers |
| dc.subject.other | Concurrent specifications |
| dc.subject.other | Signal transition graphs |
| dc.subject.other | 4-phase handshake controllers |
| dc.title | Specification mining for asynchronous controllers |
| dc.type | Conference report |
| dc.subject.lemac | Estructura lògica |
| dc.subject.lemac | Circuits asíncrons |
| dc.contributor.group | Universitat Politècnica de Catalunya. ALBCOM - Algorismia, Bioinformàtica, Complexitat i Mètodes Formals |
| dc.identifier.doi | 10.1109/ASYNC.2016.10 |
| dc.description.peerreviewed | Peer Reviewed |
| dc.relation.publisherversion | http://ieeexplore.ieee.org/document/7584900/ |
| dc.rights.access | Open Access |
| local.identifier.drac | 19241345 |
| dc.description.version | Postprint (author's final draft) |
| local.citation.author | San Pedro, J. de; Bourgeat, T.; Cortadella, J. |
| local.citation.contributor | IEEE International Symposium on Asynchronous Circuits and Systems |
| local.citation.pubplace | Porto Alegre |
| local.citation.publicationName | 22nd IEEE International Symposium on Asynchronous Circuits and Systems: 8-11 May 2016 Porto Alegre, Brazil: proceedings |
| local.citation.startingPage | 107 |
| local.citation.endingPage | 114 |
