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dc.contributor.authorJalle Ibarra, Javier
dc.contributor.authorAbella Ferrer, Jaume
dc.contributor.authorFossati, Luca
dc.contributor.authorZulianello, Marco
dc.contributor.authorCazorla Almeida, Francisco Javier
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2017-01-19T13:43:11Z
dc.date.available2017-01-19T13:43:11Z
dc.date.issued2016
dc.identifier.citationJalle, J., Abella, J., Fossati, L., Zulianello, M., Cazorla, F. Validating a timing simulator for the NGMP multicore processor. A: Data Systems in Aerospace Conference. "Proceedings of DASIA 2016: Data Systems in Aerospace, 10-12 May 2016, Tallinn, Estonia". Tallinn: European Space Agency (ESA), 2016, p. 1-5.
dc.identifier.isbn789292213015
dc.identifier.urihttp://hdl.handle.net/2117/99694
dc.description.abstractTiming simulation is a key element in multicore systems design. It enables a fast and cost effective design space exploration, allowing to simulate new architectural improvements without requiring RTL abstraction levels. Timing simulation also allows software developers to perform early testing of the timing behavior of their software without the need of buying the actual physical board, which can be very expensive when the board uses non-COTS technology. In this paper we present the validation of a timing simulator for the NGMP multicore processor, which is a 4 core processor being developed to become the reference platform for future missions of the European Space Agency.
dc.description.sponsorshipThe research leading to these results has received funding from the European Space Agency under contract NPI 4000102880 and the Ministry of Science and Technology of Spain under contract TIN-2015-65316-P. Jaume Abella has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717.
dc.format.extent5 p.
dc.language.isoeng
dc.publisherEuropean Space Agency (ESA)
dc.subjectÀrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
dc.subject.lcshComputer programs -- Testing
dc.subject.lcshIntegrated circuits -- Design and construction
dc.subject.otherCost effectiveness
dc.subject.otherIntegrated circuit design
dc.subject.otherSoftware testing
dc.subject.otherSpace flight
dc.subject.otherSystems analysis
dc.subject.otherTiming circuits
dc.subject.otherAbstraction level
dc.subject.otherArchitectural improvements
dc.subject.otherCost effective design
dc.subject.otherEuropean Space Agency
dc.subject.otherMulti-core processor
dc.subject.otherMulti-core systems
dc.subject.otherSoftware developer
dc.subject.otherTiming simulations
dc.titleValidating a timing simulator for the NGMP multicore processor
dc.typeConference report
dc.subject.lemacProgrames d'ordinador -- Control de qualitat
dc.subject.lemacCircuits integrats -- Disseny i construcció
dc.contributor.groupUniversitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions
dc.description.peerreviewedPeer Reviewed
dc.rights.accessOpen Access
drac.iddocument19286595
dc.description.versionPostprint (author's final draft)
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/1PE/TIN2015-65316-P
dc.relation.projectidinfo:eu-repo/grantAgreement/MINECO/RYC-2013-14717
upcommons.citation.authorJalle, J., Abella, J., Fossati, L., Zulianello, M., Cazorla, F.
upcommons.citation.contributorData Systems in Aerospace Conference
upcommons.citation.pubplaceTallinn
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of DASIA 2016: Data Systems in Aerospace, 10-12 May 2016, Tallinn, Estonia
upcommons.citation.startingPage1
upcommons.citation.endingPage5


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