Modelling probabilistic cache representativeness in the presence of arbitrary access patterns
Visualitza/Obre
Cita com:
hdl:2117/99586
Tipus de documentText en actes de congrés
Data publicació2016
EditorInstitute of Electrical and Electronics Engineers (IEEE)
Condicions d'accésAccés obert
Tots els drets reservats. Aquesta obra està protegida pels drets de propietat intel·lectual i
industrial corresponents. Sense perjudici de les exempcions legals existents, queda prohibida la seva
reproducció, distribució, comunicació pública o transformació sense l'autorització del titular dels drets
ProjecteRYC-2013-14717 (MINECO-RYC-2013-14717)
COMPUTACION DE ALTAS PRESTACIONES VII (MINECO-TIN2015-65316-P)
HiPEAC - High Performance and Embedded Architecture and Compilation (EC-H2020-687698)
COMPUTACION DE ALTAS PRESTACIONES VII (MINECO-TIN2015-65316-P)
HiPEAC - High Performance and Embedded Architecture and Compilation (EC-H2020-687698)
Abstract
Measurement-Based Probabilistic Timing Analysis (MBPTA) is a promising powerful industry-friendly method to derive worst-case execution time (WCET) estimates as needed for critical real-time embedded systems. MBPTA performs several (R) runs of the program on the target platform collecting the execution times in each run. MBPTA builds a probabilistic representativeness argument on whether those events with high impact on execution time, such as cache misses, arise on the runs made at analysis time so that their impact on execution time is captured. So far only events occurring in cache memories have been shown to challenge providing such representativeness argument.
In this context, this paper introduces a representativeness validation method (RVS) to assess the probabilistic representativeness of MBPTA’s execution time observations in terms of cache behaviour. RVS resorts to cache simulation to predict worst-case miss scenarios that can appear during the
deployment phase. RVS also constructs a probabilistic Worst-Case Miss Count curve based on the miss-counts captured in the R runs. If that curve upperbounds the impact of the predicted cache worst-case scenarios, R is deemed as a sufficient number of runs for which pWCET estimates can be reliably derived. Otherwise, the user is requested to perform more runs until all cache scenarios of interest are captured.
CitacióMilutinovic, S., Abella, J., Cazorla, F. Modelling probabilistic cache representativeness in the presence of arbitrary access patterns. A: IEEE International Symposium on Real-Time Distributed Computing. "2016 IEEE 19th International Symposium on Real-Time Distributed Computing, ISORC 2016: 17-20 May 2016, York, United Kingdom: proceedings". York: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 142-149.
ISBN978-1-4673-9032-3
Versió de l'editorhttp://ieeexplore.ieee.org/document/7515622/
Fitxers | Descripció | Mida | Format | Visualitza |
---|---|---|---|---|
Modelling+Proba ... che+Representativeness.pdf | 1,462Mb | Visualitza/Obre |