Random Modulo: A new processor cache design for real-time critical systems
Document typeConference lecture
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
European Commission's projectHiPEAC - High Performance and Embedded Architecture and Compilation (EC-H2020-687698)
Cache memories have a huge impact on software's worst-case execution time (WCET). While enabling the seamless use of caches is key to provide the increasing levels of (guaranteed) performance required by automotive software, caches complicate timing analysis. In the context of Measurement-Based Probabilistic Timing Analysis (MBPTA) - a promising technique to ease timing analyis of complex hardware - we propose Random Modulo (RM), a new cache design that provides the probabilistic behavior required by MBPTA and with the following advantages over existing MBPTA-compliant cache designs: (i) an outstanding reduction in WCET estimates, (ii) lower latency and area overhead, and (iii) competitive average performance w.r.t conventional caches.
CitationHernández, C., Abella, J., Gianarro, A., Andersson, J., Cazorla, F. Random Modulo: A new processor cache design for real-time critical systems. A: Design Automation Conference. "Proceedings of the 2016 53rd ACM/EDAC/IEEE Design Automation Conference (DAC)". Austin, TX: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1-6.
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