On the parallelization of slice-based Keccak implementations on Xilinx FPGAs
Document typeConference report
Rights accessOpen Access
This work explores the parallelization of slice-based lightweight Keccak implementations. The functionality of Xilinx FPGAs to use a single slice as a 32-bit Shift Register Lookup table (SRL) was recently used by Winderickx et al.  to implement Keccak. This implementation resulted in the smallest Keccak implementation, given that a custom interface was used. To enhance the implementation, we explore the parallelization of the datapath. Four datapath widths are used: 25, 50, 100 and 200 bits. The implementations with a datapath width of 25 and 50 bits give better area and throughput results than other slice-based lightweight Keccak implementations; larger datapath widths result in an inefficient usage of the SRL functionality. Furthermore, the custom interface with datapath widths larger than 50 bits is not compatible with 64-bit microprocessors and is therefore unusable in practical scenarios. The standard-compliant implementations perform worse than other slice-based lightweight Keccak implementations for all datapath widths.