dc.contributor.author | Nejat, Arash |
dc.contributor.author | Hely, David |
dc.contributor.author | Beroulle, Vincent |
dc.coverage.spatial | east=2.11563799999999; north=41.38479239999999; name=Zona Universitària-Escola T S d'Enginyers, 08028 Barcelona, Espanya |
dc.date.accessioned | 2017-01-16T11:55:38Z |
dc.date.available | 2017-01-16T11:55:38Z |
dc.date.issued | 2016-11-16 |
dc.identifier.uri | http://hdl.handle.net/2117/99303 |
dc.description.abstract | Hardware Trojan (HT) and Integrated Circuit
(IC)/ Intellectual Property (IP) piracy are important threats
which may happen in untrusted fabrication foundries. Modifying
structurally the ICs/IPs design to counter the HT threats has
been proposed, and it is known as Design-For-Hardware-Trust
(DFHT). DFHT methods are used in order to facilitate HT
detection methods. In addition, logic masking methods modify
the IPs/ICs design to harden them against the IP/IC piracy.
These methods modify a circuit such that it does not work
correctly without applying the correct key. In this paper, we
propose DFHT methods leveraging logic masking approach. |
dc.format.extent | 2 p. |
dc.language.iso | eng |
dc.rights | Attribution-NonCommercial-NoDerivs 3.0 Spain |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica |
dc.subject.lcsh | Embedded computer systems--Congresses |
dc.subject.lcsh | Integrated circuits |
dc.subject.lcsh | Computer networks--Security measures |
dc.title | Reusing Logic Masking to Facilitate Hardware Trojan Detection |
dc.type | Conference report |
dc.subject.lemac | Sistemes integrats -- Congressos |
dc.subject.lemac | Circuits integrats |
dc.subject.lemac | Seguretat informàtica -- Congressos |
dc.rights.access | Open Access |