A comparison of PUF cores suitable for FPGA devices
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A PUF extracts a unique identifier per die using physical random variation caused by variability of the manufacturing process. PUFs can be used for hardware authentication, but also as generators of confidential keys. This paper presents the comparison of RO-PUF and TERO-PUF cores implemented on Xilinx Spartan 6 FPGA. The objective is to evaluate their design when operating at the same conditions. We show that no ideal PUF exists and therefore designers will always have to choose the PUF matching the security application. In addition to design parameters like area, number of bits per challenge and power consumption, we discuss the feasibility of the design in FPGAs. This will help designers select the best PUF according to their requirements.