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dc.contributor.authorLaban, Marek
dc.contributor.authorDrutarovsky, Milos
dc.contributor.authorFischer, Viktor
dc.contributor.authorVarchola, Michal
dc.coverage.spatialeast=2.11563799999999; north=41.38479239999999; name=Zona Universitària-Escola T S d'Enginyers, 08028 Barcelona, Espanya
dc.date.accessioned2017-01-13T10:45:29Z
dc.date.available2017-01-13T10:45:29Z
dc.date.issued2016-11-16
dc.identifier.urihttp://hdl.handle.net/2117/99208
dc.description.abstractImplementation of cryptographic primitives like Physical Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) depends significantly on the underlying hardware. Common evaluation boards offered by FPGA vendors are not suitable for a fair benchmarking, since they have different vendor dependent configuration and contain noisy switching power supplies. The proposed hardware platform is primary aimed at testing and evaluation of cryptographic primitives across different FPGA and ASIC families. The modular platform consists of a motherboard and exchangeable daughter board modules. These are designed to be as simple as possible to allow cheap and independent evaluation of cryptographic blocks and namely PUFs. The motherboard is based on the Microsemi SmartFusion 2 SoC FPGA. It features a low-noise power supply, which simplifies evaluation of vulnerability to the side channel attacks. It provides also means of communication between the PC and the daughter module. Available software tools can be easily customized, for example to collect data from the random number generator located in the daughter module and to read it via USB interface. The daughter module can be plugged into the motherboard or connected using an HDMI cable to be placed inside a Faraday cage or a temperature control chamber. The whole platform was designed and optimized to fullfil the European HECTOR project (H2020) requirements.
dc.format.extent6 p.
dc.language.isoeng
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 Spain
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica
dc.subject.lcshEmbedded computer systems--Congresses
dc.subject.lcshIntegrated circuits
dc.subject.lcshComputer networks--Security measures
dc.titlePlatform for Testing and Evaluation of PUF and TRNG Implementations in FPGAs
dc.typeConference report
dc.subject.lemacSistemes integrats -- Congressos
dc.subject.lemacCircuits integrats
dc.subject.lemacSeguretat informàtica -- Congressos
dc.rights.accessOpen Access
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/H2020/644052/EU/HARDWARE ENABLED CRYPTO AND RANDOMNESS/HECTOR


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Except where otherwise noted, content on this work is licensed under a Creative Commons license: Attribution-NonCommercial-NoDerivs 3.0 Spain