MUSA: a multi-level simulation approach for next-generation HPC machines
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
European Commisision's projectROMOL - Riding on Moore's Law (EC-FP7-321253)
Mont-Blanc 3 - Mont-Blanc 3, European scalable and power efficient HPC platformbased on low-power embedded technology (EC-H2020-671697)
The complexity of High Performance Computing (HPC) systems is increasing in the number of components and their heterogeneity. Interactions between software and hardware involve many different aspects which are typically not transparent to scientific programmers and system architects. Therefore, predicting the behavior of current scientific applications on future HPC infrastructures is a challenging task. In this paper we present MUSA, an end-to-end methodology that employs a multi-level simulation infrastructure. By combining different levels of abstraction, MUSA is able to model the communication network, microarchitectural details and system software interactions, providing different trade-offs in terms of simulation cost and accuracy. We compare detailed MUSA simulations with native executions of up to 2,048 cores and find relative errors that are within 10% in the common case. In addition, we use MUSA to simulate up to 16,384 cores and successfully identify scalability bottlenecks due to different factors, e.g. memory contention or load imbalance. We also compare different system configurations, showing how MUSA can help system designers to assess the usefulness of future technologies in next-generation HPC machines.
CitationGrass, T., Allande, C., Armejach, A., Rico, A., Ayguade, E., Labarta, J., Valero, M., Casas, M., Moreto, M. MUSA: a multi-level simulation approach for next-generation HPC machines. A: International Conference for High Performance Computing, Networking, Storage and Analysis. "SC'16: International Conference for High Performance Computing, Networking, Storage and Analysis: proceedings: Salt Lake City, UT, USA: November 13-18, 2016". Salt Lake City, UT: Institute of Electrical and Electronics Engineers (IEEE), 2016.
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