Mostra el registre d'ítem simple
Leveraging register windows to reduce physical registers to the bare minimum
dc.contributor.author | Quiñones, Eduardo |
dc.contributor.author | Parcerisa Bundó, Joan Manuel |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2017-01-12T05:57:14Z |
dc.date.available | 2017-01-12T05:57:14Z |
dc.date.issued | 2010-12 |
dc.identifier.citation | Quiñones, E., Parcerisa, J.M, González, A. Leveraging register windows to reduce physical registers to the bare minimum. "IEEE transactions on computers", Desembre 2010, vol. 59, núm. 12, p. 1598-1610. |
dc.identifier.issn | 0018-9340 |
dc.identifier.uri | http://hdl.handle.net/2117/99067 |
dc.description.abstract | Register window is an architectural technique that reduces memory operations required to save and restore registers across procedure calls. Its effectiveness depends on the size of the register file. Such register requirements are normally increased for out-of-order execution because it requires registers for the in-flight instructions, in addition to the architectural ones. However, a large register file has an important cost in terms of area and power and may even affect the cycle time. In this paper, we propose a software/hardware early register release technique that leverage register windows to drastically reduce the register requirements, and hence, reduce the register file cost. Contrary to the common belief that out-of-order processors with register windows would need a large physical register file, this paper shows that the physical register file size may be reduced to the bare minimum by using this novel microarchitecture. Moreover, our proposal has much lower hardware complexity than previous approaches, and requires minimal changes to a conventional register window scheme. Performance studies show that the proposed technique can reduce the number of physical registers to the number of logical registers plus one (minimum number to guarantee forward progress) and still achieve almost the same performance as an unbounded register file. |
dc.format.extent | 13 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Enginyeria del software |
dc.subject.lcsh | Software architecture |
dc.subject.lcsh | File organization (Computer science) |
dc.subject.other | Register windows |
dc.subject.other | Physical register file |
dc.subject.other | Early register release |
dc.title | Leveraging register windows to reduce physical registers to the bare minimum |
dc.type | Article |
dc.subject.lemac | Programari -- Disseny |
dc.subject.lemac | Fitxers informàtics -- Organització |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/TC.2010.85 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/5453344/?arnumber=5453344 |
dc.rights.access | Open Access |
local.identifier.drac | 4506677 |
dc.description.version | Postprint (published version) |
local.citation.author | Quiñones, E.; Parcerisa, J.M; González, A. |
local.citation.publicationName | IEEE transactions on computers |
local.citation.volume | 59 |
local.citation.number | 12 |
local.citation.startingPage | 1598 |
local.citation.endingPage | 1610 |
Fitxers d'aquest items
Aquest ítem apareix a les col·leccions següents
-
Articles de revista [1.049]
-
Articles de revista [68]