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Late allocation and early release of physical registers
dc.contributor.author | Monreal Arnal, Teresa |
dc.contributor.author | Viñals Yufera, Víctor |
dc.contributor.author | González González, José |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.author | Valero Cortés, Mateo |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2016-12-15T14:22:53Z |
dc.date.available | 2016-12-15T14:22:53Z |
dc.date.issued | 2004-10 |
dc.identifier.citation | Monreal, T., Viñals, V., González, J., González, A., Valero, M. Late allocation and early release of physical registers. "IEEE transactions on computers", Octubre 2004, vol. 53, núm. 10, p. 1244-1259. |
dc.identifier.issn | 0018-9340 |
dc.identifier.uri | http://hdl.handle.net/2117/98349 |
dc.description.abstract | The register file is one of the critical components of current processors in terms of access time and power consumption. Among other things, the potential to exploit instruction-level parallelism is closely related to the size and number of ports of the register file. In conventional register renaming schemes, both register allocation and releasing are conservatively done, the former at the rename stage, before registers are loaded with values, and the latter at the commit stage of the instruction redefining the same register, once registers are not used any more. We introduce VP-LAER, a renaming scheme that allocates registers later and releases them earlier than conventional schemes. Specifically, physical registers are allocated at the end of the execution stage and released as soon as the processor realizes that there will be no further use of them. VP-LAER enhances register utilization, that is, the fraction of allocated registers having a value to be read in the future. Detailed cycle-level simulations show either a significant speedup for a given register file size or a reduction in the register file size for a given performance level, especially for floating-point codes, where the register file pressure is usually high. |
dc.format.extent | 16 p. |
dc.language.iso | eng |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Parallel processing (Electronic computers) |
dc.subject.other | Register renaming |
dc.subject.other | Out-of-order processors |
dc.subject.other | Register file optimization |
dc.subject.other | Physical register allocation and releasing |
dc.subject.other | Precise exceptions |
dc.title | Late allocation and early release of physical registers |
dc.type | Article |
dc.subject.lemac | Processament en paral·lel (Ordinadors) |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/TC.2004.79 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/1327576/ |
dc.rights.access | Open Access |
local.identifier.drac | 654641 |
dc.description.version | Postprint (published version) |
local.citation.author | Monreal, T.; Viñals, V.; González, J.; González, A.; Valero, M. |
local.citation.publicationName | IEEE transactions on computers |
local.citation.volume | 53 |
local.citation.number | 10 |
local.citation.startingPage | 1244 |
local.citation.endingPage | 1259 |
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