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Modeling high-performance wormhole NoCs for critical real-time embedded systems
dc.contributor.author | Panic, Milos |
dc.contributor.author | Hernández, Carles |
dc.contributor.author | Quiñones, Eduardo |
dc.contributor.author | Abella Ferrer, Jaume |
dc.contributor.author | Cazorla Almeida, Francisco Javier |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.contributor.other | Barcelona Supercomputing Center |
dc.date.accessioned | 2016-12-15T10:11:44Z |
dc.date.available | 2016-12-15T10:11:44Z |
dc.date.issued | 2016 |
dc.identifier.citation | Panic, M., Hernández, C., Quiñones, E., Abella, J., Cazorla, F. Modeling high-performance wormhole NoCs for critical real-time embedded systems. A: IEEE Real-Time and Embedded Technology and Applications Symposium. "2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS): 11-14 April 2016: Vienna, Austria: proceedings". Vienna: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1-12. |
dc.identifier.isbn | 9781467386395 |
dc.identifier.uri | http://hdl.handle.net/2117/98317 |
dc.description.abstract | Manycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's timing behavior when their requests use manycore's network-on-chip (NoC) to access hardware shared resources. This paper analyzes the contention in wormhole-based NoC (wNoC) designs - widely implemented in the high-performance domain - for which we introduce a new metric: worst-contention delay (WCD) that captures wNoC impact on worst-case execution time (WCET) in a tighter manner than the existing metric, worst-case traversal time (WCTT). Moreover, we provide an analytical model of the WCD that requests can suffer in a wNoC and we validate it against wNoC designs resembling those in the Tilera-Gx36 and the Intel-SCC 48-core processors. Building on top of our WCD analytical model, we analyze the impact on WCD that different design parameters such as the number of virtual channels, and we make a set of recommendations on what wNoC setups to use in the context of CRTES. |
dc.format.extent | 12 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.subject | Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors |
dc.subject.lcsh | Multiprocessors |
dc.subject.lcsh | Embedded computer systems |
dc.subject.lcsh | Logic design |
dc.subject.other | Analytical models |
dc.subject.other | Network-on-chip |
dc.subject.other | Real time systems |
dc.subject.other | VLSI circuits |
dc.subject.other | Computing platform |
dc.subject.other | Design parameters |
dc.subject.other | Network-on-chip(NoC) |
dc.subject.other | Real-time embedded systems |
dc.subject.other | Shared resources |
dc.subject.other | Traversal time |
dc.subject.other | Virtual channels |
dc.subject.other | Worst-case execution time |
dc.title | Modeling high-performance wormhole NoCs for critical real-time embedded systems |
dc.type | Conference report |
dc.subject.lemac | Multiprocessadors |
dc.subject.lemac | Ordinadors immersos, Sistemes d' |
dc.subject.lemac | Estructura lògica |
dc.contributor.group | Universitat Politècnica de Catalunya. CAP - Grup de Computació d'Altes Prestacions |
dc.identifier.doi | 10.1109/RTAS.2016.7461342 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7461342 |
dc.rights.access | Open Access |
local.identifier.drac | 18766224 |
dc.description.version | Postprint (author's final draft) |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TIN2015-65316-P/ES/COMPUTACION DE ALTAS PRESTACIONES VII/ |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//TIN2014-60404-JIN/ES/PROBABILISTIC TIMING ANALYSIS OF HIGH-PERFORMANCE AND RELIABLE PROCESSORS/ |
dc.relation.projectid | info:eu-repo/grantAgreement/MINECO//RYC-2013-14717/ES/RYC-2013-14717/ |
local.citation.author | Panic, M.; Hernández, C.; Quiñones, E.; Abella, J.; Cazorla, F. |
local.citation.contributor | IEEE Real-Time and Embedded Technology and Applications Symposium |
local.citation.pubplace | Vienna |
local.citation.publicationName | 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS): 11-14 April 2016: Vienna, Austria: proceedings |
local.citation.startingPage | 1 |
local.citation.endingPage | 12 |