Modeling high-performance wormhole NoCs for critical real-time embedded systems
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessOpen Access
Manycore chips are a promising computing platform to cope with the increasing performance needs of critical real-time embedded systems (CRTES). However, manycores adoption by CRTES industry requires understanding task's timing behavior when their requests use manycore's network-on-chip (NoC) to access hardware shared resources. This paper analyzes the contention in wormhole-based NoC (wNoC) designs - widely implemented in the high-performance domain - for which we introduce a new metric: worst-contention delay (WCD) that captures wNoC impact on worst-case execution time (WCET) in a tighter manner than the existing metric, worst-case traversal time (WCTT). Moreover, we provide an analytical model of the WCD that requests can suffer in a wNoC and we validate it against wNoC designs resembling those in the Tilera-Gx36 and the Intel-SCC 48-core processors. Building on top of our WCD analytical model, we analyze the impact on WCD that different design parameters such as the number of virtual channels, and we make a set of recommendations on what wNoC setups to use in the context of CRTES.
CitationPanic, M., Hernández, C., Quiñones, E., Abella, J., Cazorla, F. Modeling high-performance wormhole NoCs for critical real-time embedded systems. A: IEEE Real-Time and Embedded Technology and Applications Symposium. "2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS): 11-14 April 2016: Vienna, Austria: proceedings". Vienna: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 1-12.
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