ASIC implementation of an all-digital self-adaptive PVTA variation-aware clock generation system
Document typeConference report
PublisherAssociation for Computing Machinery (ACM)
Rights accessRestricted access - publisher's policy
An all-digital self-adaptive clock generation system capable of autonomously adapt the clock frequency to compensate the effects of static spatially heterogeneous (SSHet) PVTA variations is presented. The design uses timeto-digital converters (TDCs) as delay sensors and a variable length ring oscillator (VLRO) as clock generator. The VLRO naturally adapts its frequency to the PVTA variations suffered by its logic gates while the TDCs are used to track these variations across the chip and modify the VLRO length in order to allocate them. The proposed system has been implemented in a silicon chip using a 65nm process. The fabricated chip has been used to test the system adaptive capabilities under SSHet voltage variations. Measurement results show that it effectively adapts the VLRO length, and hence the clock frequency, to the supply voltage variations.
CitationPérez-Puigdemont, J., Moll, F. ASIC implementation of an all-digital self-adaptive PVTA variation-aware clock generation system. A: ACM Great Lakes Symposium on VLSI. "GLSVLSI'16: proceedings of the 2016 ACM Great Lakes Symposium on VLSI: May 18-20, 2016: Boston, MA, USA". Boston, Massachusetts: Association for Computing Machinery (ACM), 2016, p. 381-384.
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