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dc.contributor.authorRiera Villanueva, Marc
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorAbella, Jaume
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.identifier.citationRiera, M., Canal, R., Abella, J., Gonzalez, A. A detailed methodology to compute soft error rates in advanced technologies. A: Design, Automation & Test in Europe Conference & Exhibition. "Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE): 14-18 March 2016, ICC, Dresden, Germany". Dresden: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 217-222.
dc.description.abstractSystem reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the technology used to build hardware. However, there is a lack of detailed methodologies to model and fairly compare Soft Error Rates (SER) across different advanced technologies. This work first describes a common methodology that from (1) technology models, (2) location (latitude, longitude and altitude), (3) operating conditions and (4) circuit descriptions (i.e. SRAM, latches, logic gates) can obtain accurate Soft Error Rates. Then, we use it to characterize soft errors through current and future technologies. Results at the technology layer show that new technologies, such as FinFET and SOI, can reduce SER up to 100x while the location can increase SER up to 650x. © 2016 EDAA.
dc.description.sponsorshipThis work has been partially supported by the Spanish Ministry of Education and Science under grant TIN2013-44375-R and the FP7 program of the EU under contract FP7-611404 (CLERECO). Jaume Abella has been partially supported by the Ministry of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship number RYC-2013-14717.
dc.format.extent6 p.
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subjectÀrees temàtiques de la UPC::Informàtica
dc.subject.lcshIntegrated circuits
dc.subject.lcshSoftware engineering
dc.subject.otherError correction
dc.subject.otherRadiation hardening
dc.subject.otherReconfigurable hardware
dc.subject.otherAdvanced technology
dc.subject.otherCircuit description
dc.subject.otherFuture technologies
dc.subject.otherOperating condition
dc.subject.otherSoft error rate
dc.subject.otherSystem reliability
dc.subject.otherThrough current
dc.subject.otherTransient faults
dc.titleA detailed methodology to compute soft error rates in advanced technologies
dc.typeConference report
dc.subject.lemacCircuits integrats
dc.subject.lemacEnginyeria de programari
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.description.peerreviewedPeer Reviewed
dc.rights.accessRestricted access - publisher's policy
dc.description.versionPostprint (published version)
dc.relation.projectidinfo:eu-repo/grantAgreement/EC/FP7/611404/EU/Cross-Layer Early Reliability Evaluation for the Computing cOntinuum/CLERECO
upcommons.citation.authorRiera, M.; Canal, R.; Abella, J.; Gonzalez, A.
upcommons.citation.contributorDesign, Automation & Test in Europe Conference & Exhibition
upcommons.citation.publicationNameProceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE): 14-18 March 2016, ICC, Dresden, Germany

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