A detailed methodology to compute soft error rates in advanced technologies
Document typeConference report
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Rights accessRestricted access - publisher's policy
European Commisision's projectCLERECO - Cross-Layer Early Reliability Evaluation for the Computing cOntinuum (EC-FP7-611404)
System reliability has become a key design aspect for computer systems due to the aggressive technology miniaturization. Errors are typically dominated by transient faults due to radiation and are strongly related to the technology used to build hardware. However, there is a lack of detailed methodologies to model and fairly compare Soft Error Rates (SER) across different advanced technologies. This work first describes a common methodology that from (1) technology models, (2) location (latitude, longitude and altitude), (3) operating conditions and (4) circuit descriptions (i.e. SRAM, latches, logic gates) can obtain accurate Soft Error Rates. Then, we use it to characterize soft errors through current and future technologies. Results at the technology layer show that new technologies, such as FinFET and SOI, can reduce SER up to 100x while the location can increase SER up to 650x. © 2016 EDAA.
CitationRiera, M., Canal, R., Abella, J., Gonzalez, A. A detailed methodology to compute soft error rates in advanced technologies. A: Design, Automation & Test in Europe Conference & Exhibition. "Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE): 14-18 March 2016, ICC, Dresden, Germany". Dresden: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 217-222.