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dc.contributor.authorAnglada Sánchez, Martí
dc.contributor.authorCanal Corretger, Ramon
dc.contributor.authorAragon, Juan Luis
dc.contributor.authorGonzález Colás, Antonio María
dc.contributor.otherUniversitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
dc.date.accessioned2016-12-01T13:39:43Z
dc.date.issued2016
dc.identifier.citationAnglada, M., Canal, R., Aragon, J., Gonzalez, A. MASkIt: soft error rate estimation for combinatorial circuits. A: IEEE International Conference on Computer Design. "Proceedings of the 34th IEEE International Conference on Computer Design (ICCD): October 2-5, 2016: Scottsdale, AZ, USA". Scottsdale, AZ: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 614-621.
dc.identifier.isbn978-1-5090-5143-4
dc.identifier.urihttp://hdl.handle.net/2117/97620
dc.description.abstractIntegrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation of combinational circuits is presented. The proposed framework is divided in two stages. First, signal probabilities are computed via a hybrid approach combining heuristics and selective simulation of reconvergent subnets. In the second stage, signal probabilities are used to compute the vulnerability of all the gates in a combinational block using a backward-traversing algorithm that takes into account logical, electrical and timing masking factors. Experimental results show that our signal probability estimation approach, in comparison with similar techniques in the literature, reduces inaccuracy by 96% while adding minimal execution time overhead. In addition, results indicate that our framework is two orders of magnitude faster than traditional Monte Carlo-based fault injection with minor loss in accuracy in both signal probability and SER estimation (average error of 5%).
dc.format.extent8 p.
dc.language.isoeng
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/es/
dc.subjectÀrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats
dc.subjectÀrees temàtiques de la UPC::Matemàtiques i estadística::Anàlisi matemàtica
dc.subject.lcshIntegrated circuits
dc.subject.lcshError analysis (Mathematics)
dc.subject.otherLogic gates
dc.subject.otherEstimation
dc.subject.otherHeuristic algorithms
dc.subject.otherIntegrated circuit modeling
dc.subject.otherAlgorithm design and analysis
dc.subject.otherCircuit faults
dc.subject.otherError analysis
dc.titleMASkIt: soft error rate estimation for combinatorial circuits
dc.typeConference report
dc.subject.lemacCircuits integrats
dc.subject.lemacAnàlisi d'error (Matemàtica)
dc.contributor.groupUniversitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors
dc.identifier.doi10.1109/ICCD.2016.7753348
dc.description.peerreviewedPeer Reviewed
dc.relation.publisherversionhttp://ieeexplore.ieee.org/document/7753348/
dc.rights.accessRestricted access - publisher's policy
drac.iddocument19267306
dc.description.versionPostprint (published version)
dc.date.lift10000-01-01
upcommons.citation.authorAnglada, M.; Canal, R.; Aragon, J.; Gonzalez, A.
upcommons.citation.contributorIEEE International Conference on Computer Design
upcommons.citation.pubplaceScottsdale, AZ
upcommons.citation.publishedtrue
upcommons.citation.publicationNameProceedings of the 34th IEEE International Conference on Computer Design (ICCD): October 2-5, 2016: Scottsdale, AZ, USA
upcommons.citation.startingPage614
upcommons.citation.endingPage621


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