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MASkIt: soft error rate estimation for combinatorial circuits
dc.contributor.author | Anglada Sánchez, Martí |
dc.contributor.author | Canal Corretger, Ramon |
dc.contributor.author | Aragon, Juan Luis |
dc.contributor.author | González Colás, Antonio María |
dc.contributor.other | Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors |
dc.date.accessioned | 2016-12-01T13:39:43Z |
dc.date.issued | 2016 |
dc.identifier.citation | Anglada, M., Canal, R., Aragon, J., Gonzalez, A. MASkIt: soft error rate estimation for combinatorial circuits. A: IEEE International Conference on Computer Design. "Proceedings of the 34th IEEE International Conference on Computer Design (ICCD): October 2-5, 2016: Scottsdale, AZ, USA". Scottsdale, AZ: Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 614-621. |
dc.identifier.isbn | 978-1-5090-5143-4 |
dc.identifier.uri | http://hdl.handle.net/2117/97620 |
dc.description.abstract | Integrated circuits are getting increasingly vulnerable to soft errors; as a consequence, soft error rate (SER) estimation has become an important and very challenging goal. In this work, a novel approach for SER estimation of combinational circuits is presented. The proposed framework is divided in two stages. First, signal probabilities are computed via a hybrid approach combining heuristics and selective simulation of reconvergent subnets. In the second stage, signal probabilities are used to compute the vulnerability of all the gates in a combinational block using a backward-traversing algorithm that takes into account logical, electrical and timing masking factors. Experimental results show that our signal probability estimation approach, in comparison with similar techniques in the literature, reduces inaccuracy by 96% while adding minimal execution time overhead. In addition, results indicate that our framework is two orders of magnitude faster than traditional Monte Carlo-based fault injection with minor loss in accuracy in both signal probability and SER estimation (average error of 5%). |
dc.format.extent | 8 p. |
dc.language.iso | eng |
dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/3.0/es/ |
dc.subject | Àrees temàtiques de la UPC::Enginyeria electrònica::Microelectrònica::Circuits integrats |
dc.subject | Àrees temàtiques de la UPC::Matemàtiques i estadística::Anàlisi matemàtica |
dc.subject.lcsh | Integrated circuits |
dc.subject.lcsh | Error analysis (Mathematics) |
dc.subject.other | Logic gates |
dc.subject.other | Estimation |
dc.subject.other | Heuristic algorithms |
dc.subject.other | Integrated circuit modeling |
dc.subject.other | Algorithm design and analysis |
dc.subject.other | Circuit faults |
dc.subject.other | Error analysis |
dc.title | MASkIt: soft error rate estimation for combinatorial circuits |
dc.type | Conference report |
dc.subject.lemac | Circuits integrats |
dc.subject.lemac | Anàlisi d'error (Matemàtica) |
dc.contributor.group | Universitat Politècnica de Catalunya. ARCO - Microarquitectura i Compiladors |
dc.identifier.doi | 10.1109/ICCD.2016.7753348 |
dc.description.peerreviewed | Peer Reviewed |
dc.relation.publisherversion | http://ieeexplore.ieee.org/document/7753348/ |
dc.rights.access | Restricted access - publisher's policy |
local.identifier.drac | 19267306 |
dc.description.version | Postprint (published version) |
dc.date.lift | 10000-01-01 |
local.citation.author | Anglada, M.; Canal, R.; Aragon, J.; Gonzalez, A. |
local.citation.contributor | IEEE International Conference on Computer Design |
local.citation.pubplace | Scottsdale, AZ |
local.citation.publicationName | Proceedings of the 34th IEEE International Conference on Computer Design (ICCD): October 2-5, 2016: Scottsdale, AZ, USA |
local.citation.startingPage | 614 |
local.citation.endingPage | 621 |