POSTER: an integrated vector-scalar design on an in-order ARM core
Document typeConference report
PublisherAssociation for Computing Machinery (ACM)
Rights accessRestricted access - publisher's policy
European Commisision's projectROMOL - Riding on Moore's Law (EC-FP7-321253)
In the low-end mobile processor market, power, energy and area budgets are significantly lower than in other markets (e.g. servers or high-end mobile markets). It has been shown that vector processors are a highly energyefficient way to increase performance; however adding support for them incurs area and power overheads that would not be acceptable for low-end mobile processors. In this work, we propose an integrated vector-scalar design for the ARM architecture that mostly reuses scalar hardware to support the execution of vector instructions. The key element of the design is our proposed block-based model of execution that groups vector computational instructions together to execute them in a coordinated manner.
CitationStanic, M., Palomar, O., Hayes, T., Ratkovic, I., Unsal, O., Cristal, A., Valero, M. POSTER: an integrated vector-scalar design on an in-order ARM core. A: International Conference on Parallel Architectures and Compilation Techniques. "PACT '16: Proceedings of the 2016 International Conference on Parallel Architectures and Compilation". Haifa: Association for Computing Machinery (ACM), 2016, p. 447-448.